Poul Frederick Williams

According to our database1, Poul Frederick Williams authored at least 6 papers between 1999 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2003
Satisfiability checking using Boolean Expression Diagrams.
Int. J. Softw. Tools Technol. Transf., 2003

2001
Formal Verification based on Boolean Expression Diagrams.
Electronic Notes in Theoretical Computer Science 56, Elsevier, 2001

2000
Bypassing BDD construction for reliability analysis.
Inf. Process. Lett., 2000

Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking.
Proceedings of the Computer Aided Verification, 12th International Conference, 2000

1999
Equivalence checking of combinational circuits using Boolean expression diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Equivalence checking of hierarchical combinational circuits.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999


  Loading...