Poras T. Balsara

According to our database, Poras T. Balsara authored at least 94 papers between 1986 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Intelligent Multi-Functional Fault Current Limiter.

Hesam Nourmohamadi, Ghanshyamsinh Gohil, Poras T. Balsara

IEEE Trans. Smart Grid, May, 2024

Hardware-based Detection of Malicious Firmware Modification in Microgrids.

Amisha Srivastava, Sneha Thakur, Abraham Peedikayil Kuruvila, Poras T. Balsara, Kanad Basu

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Fully Distributed Control of Microgrids Using Multi-Agent Approach.

Vaibhav Uttam Pawaskar, Poras T. Balsara, Babak Fahimi, Ghanshyamsinh Gohil

Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023

2022

A new submodule structure with parallel capacitor connection in modular multilevel converters.

G. Veera Bharath, Ghanshyamsinh Gohil, Poras T. Balsara

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2020

New Concept for Fault Current Limiter With Voltage Restoration Capability.

Hesam Nourmohamadi, Mehran Sabahi, Poras T. Balsara, Ebrahim Babaei, Seyed Hossein Hosseini, Amir Fakhim-Babaei

IEEE Trans. Ind. Electron., 2020

2018

Mitigation of Positive Zero Effect on Nonminimum Phase Boost DC-DC Converters in CCM.

Vikas V. Paduvalli, R. J. Taylor, Louis R. Hunt, Poras T. Balsara

IEEE Trans. Ind. Electron., 2018

2017

Analysis of Zeros in a Boost DC-DC Converter: State Diagram Approach.

Vikas V. Paduvalli, R. J. Taylor, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach.

Essam S. Atalla, Frank Zhang, Poras T. Balsara, Abdellatif Bellaouar, Seydou Ba, Kamran Kiasaleh

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Portable impedance measurement device for sweat based glucose detection.

Athul Asokan Thulasi, Dinesh Bhatia, Poras T. Balsara, Shalini Prasad

Proceedings of the 14th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2017

2016

A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution.

Imran Bashir, Robert Bogdan Staszewski, Poras T. Balsara

IEEE J. Solid State Circuits, 2016

A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation.

Imran Bashir, Robert Bogdan Staszewski, Oren E. Eliezer, Poras T. Balsara

J. Electron. Test., 2016

Effect of sampling time and sampling instant on the frequency response of a boost converter.

Sameer Arora, Poras T. Balsara, Dinesh K. Bhatia

Proceedings of the IECON 2016, 2016

2015

Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter.

Sujan K. Manohar, L. R. Hunt, Poras T. Balsara, Dinesh K. Bhatia, Vikas V. Paduvalli

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Envelope tracking using transient waveform switching shaping supply modulation.

Sankalp Modi, Poras T. Balsara, Oren E. Eliezer

Int. J. Circuit Theory Appl., 2015

2014

Complex QR Decomposition Using Fast Plane Rotations for MIMO Applications.

Aditya Awasthi, Rohit Guttal, Naofal Al-Dhahir, Poras T. Balsara

IEEE Commun. Lett., 2014

2013

IIP2 requirements in 4G LTE handset receivers.

Essam S. Atalla, Abdellatif Bellaouar, Poras T. Balsara

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Novel analysis of passive mixer output impedance using switched-capacitor techniques.

Essam S. Atalla, Abdellatif Bellaouar, Poras T. Balsara

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

94.6% peak efficiency DCM buck converter with fast adaptive dead-time control.

Sujan K. Manohar, Poras T. Balsara

Proceedings of the ESSCIRC 2013, 2013

Estimation of passive mixer output bandwidth using switched-capacitor techniques.

Essam S. Atalla, Frank Zhang, Abdellatif Bellaouar, Poras T. Balsara

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops.

Ioannis L. Syllaios, Poras T. Balsara

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency.

Sujan K. Manohar, Ramakrishnan Venkatasubramanian, Poras T. Balsara

Proceedings of the 25th International Conference on VLSI Design, 2012

Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management.

Sujan K. Manohar, Vinod K. Somasundar, Ramakrishnan Venkatasubramanian, Poras T. Balsara

Proceedings of the 25th International Conference on VLSI Design, 2012

Alien crosstalk mitigation in vectored DSL systems for backhaul applications.

Aditya Awasthi, Naofal Al-Dhahir, Oren E. Eliezer, Poras T. Balsara

Proceedings of IEEE International Conference on Communications, 2012

2011

A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter.

Imran Bashir, Robert Bogdan Staszewski, Oren E. Eliezer, Bhaskar Banerjee, Poras T. Balsara

IEEE J. Solid State Circuits, 2011

Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop.

Ramakrishnan Venkatasubramanian, Sujan K. Manohar, Poras T. Balsara

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Multi-clock domain analysis and modeling of all-digital frequency synthesizers.

Ioannis L. Syllaios, Poras T. Balsara

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder.

Venkata K. Kidambi Srinivasan, Chitranjan K. Singh, Poras T. Balsara

IEEE Trans. Very Large Scale Integr. Syst., 2010

Recombination of Envelope and Phase Paths in Wideband Polar Transmitters.

Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter.

Jaimin Mehta, Vasile Zoicas, Oren E. Eliezer, Robert Bogdan Staszewski, Sameh Rezeq, Mitch Entezari, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Design of a link-controller architecture for multiple serial link protocols.

Lei Wang, Pawankumar Hegde, Vishal Nawathe, Roman Staszewski, Poras T. Balsara, Vojin G. Oklobdzija

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding.

Mangesh K. Kunchamwar, Durga P. Prasad, Pawan Hegde, Poras T. Balsara, Rama Sangireddy

Proceedings of the 39th International Conference on Parallel Processing, 2010

2009

All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters.

Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation.

Imtinan Elahi, Khurram Muhammad, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers.

Oren Eytan Eliezer, Robert Bogdan Staszewski, Imran Bashir, Sumeer Bhatara, Poras T. Balsara

IEEE J. Solid State Circuits, 2009

2008

Time-Domain Modeling of an RF All-Digital PLL.

Ioannis L. Syllaios, Robert Bogdan Staszewski, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007

All-Digital PLL With Ultra Fast Settling.

Robert Bogdan Staszewski, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels.

Raghunath Cherukuri, Poras T. Balsara

Proceedings of the 66th IEEE Vehicular Technology Conference, 2007

VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition.

Chitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios.

Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski

Proceedings of the IEEE 18th International Symposium on Personal, 2007

Effect of Word-length Precision on the Performance of MIMO Systems.

Chitranjan K. Singh, Naofal Al-Dhahir, Poras T. Balsara

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters.

Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer, Jaimin Mehta

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters.

Viral K. Parikh, Poras T. Balsara, Oren E. Eliezer, Jaimin Mehta

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications.

Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS.

Robert Bogdan Staszewski, Sudheer K. Vemulapalli, Prasant Vallur, John L. Wallberg, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2006

IIP2 and DC Offsets in the Presence of Leakage at LO Frequency.

Imtinan Elahi, Khurram Muhammad, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2006

I/Q mismatch compensation using adaptive decorrelation in a low-IF receiver in 90-nm CMOS process.

Imtinan Elahi, Khurram Muhammad, Poras T. Balsara

IEEE J. Solid State Circuits, 2006

A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter.

V. Ramakrishnan, Poras T. Balsara

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Exploring Logic Block Granularity in Leakage Tolerant FPGA.

Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A generalized signal reconstruction method for designing interpolation filters.

Ioannis L. Syllaios, Poras T. Balsara, Oren E. Eliezer

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reconfigurable CAM Architecture for Network Search Engines.

Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Generic Network Interfaces for Plug and Play NoC Based Architecture.

Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005

SoC with an integrated DSP and a 2.4-GHz RF transmitter.

Robert Bogdan Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Kenneth Maggio, Poras T. Balsara

IEEE Trans. Very Large Scale Integr. Syst., 2005

Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination.

Robert Bogdan Staszewski, Dirk Leipold, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Event-driven Simulation and modeling of phase noise of an RF oscillator.

Robert Bogdan Staszewski, Chan Fernando, Poras T. Balsara

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Phase-domain all-digital phase-locked loop.

Robert Bogdan Staszewski, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Power Switch Network Design for MTCMOS.

Ramaprasath Vilangudipitchai, Poras T. Balsara

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

The Impact of Inductance on Transients Affecting Gate Oxide Reliability.

N. S. Nagaraj, William R. Hunter, Poras T. Balsara, Cyrus D. Cantrell

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

VHDL Simulation and Modeling of an All-Digital RF Transmitter.

Robert Bogdan Staszewski, Roman Staszewski, Poras T. Balsara

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA.

Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines.

Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

FPGA Architecture for Standby Power Management.

Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Exploiting temporal idleness to reduce leakage power in programmable architectures.

Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS.

Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold, Chih-Ming Hung, Yo-Chuol Ho, John L. Wallberg, Chan Fernando, Ken Maggio, Roman Staszewski, Tom Jung, Jinseok Koh, Soji John, Irene Yuanying Deng, Vivek Sarda, Oscar Moreira-Tamayo, Valerian Mayega, Ran Katz, Ofer Friedman, Oren Eytan Eliezer, Elida de-Obaldia, Poras T. Balsara

IEEE J. Solid State Circuits, 2004

Interconnect Modeling for Copper/Low-k Technologies.

N. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Event-driven simulation and modeling of an RF oscillator.

Robert Bogdan Staszewski, Chan Fernando, Poras T. Balsara

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks.

Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003

Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process.

Robert Bogdan Staszewski, Dirk Leipold, Khurram Muhammad, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation.

Robert Bogdan Staszewski, Dirk Leipold, Poras T. Balsara

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Benchmarks for Interconnect Parasitic Resistance and Capacitance.

N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002

Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification.

N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels.

Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara

IEEE Trans. Very Large Scale Integr. Syst., 2001

Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations.

Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Challenges in integrated CMOS transceivers for short distance wireless.

Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000

High-performance energy-efficient D-flip-flop circuits.

Uming Ko, Poras T. Balsara

IEEE Trans. Very Large Scale Integr. Syst., 2000

A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels.

Robert Bogdan Staszewski, Khurram Muhammad, Poras T. Balsara

IEEE J. Solid State Circuits, 2000

Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels.

Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Reconfigurable Array Media Processor (RAMP).

Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999

High performance low power array multiplier using temporal tiling.

Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds

IEEE Trans. Very Large Scale Integr. Syst., 1999

Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis.

Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

Energy optimization of multilevel cache architectures for RISC and CISC processors.

Uming Ko, Poras T. Balsara, Ashwini K. Nanda

IEEE Trans. Very Large Scale Integr. Syst., 1998

LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service.

Sharat Prasad, Kamran Kiasaleh, Poras T. Balsara

Proceedings of the Proceedings IEEE INFOCOM '98, The Conference on Computer Communications, Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies, Gateway to the 21st Century, San Francisco, CA, USA, March 29, 1998

1996

Performance of CMOS differential circuits.

Pius Ng, Poras T. Balsara, Don Steiss

IEEE J. Solid State Circuits, 1996

Leap frog multiplier.

Shivaling S. Mahant-Shetti, Carl Lemonds, Poras T. Balsara

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Design techniques for high performance, energy efficient control logic.

Uming Ko, Anthony M. Hill, Poras T. Balsara

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

Short-circuit power driven gate sizing technique for reducing power dissipation.

Uming Ko, Poras T. Balsara

IEEE Trans. Very Large Scale Integr. Syst., 1995

An architecture for a DSP field-programmable gate array.

M. Agarwala, Poras T. Balsara

IEEE Trans. Very Large Scale Integr. Syst., 1995

Hierarchy embedded differential image for progressive transmission using lossless compression.

Whoi-Yul Kim, Poras T. Balsara, David T. Harper III, Jon Wong Park

IEEE Trans. Circuits Syst. Video Technol., 1995

Energy optimization of multi-level processor cache architectures.

Uming Ko, Poras T. Balsara, Ashwini K. Nanda

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1992

Intermediate-level vision tasks on a memory array architecture.

Poras T. Balsara, Mary Jane Irwin

Mach. Vis. Appl., 1992

Design and implementation of a multi-microprocessor architecture for image processing.

Arun Vaidyanathan, Eric M. Dowling, Poras T. Balsara

Microprocess. Microsystems, 1992

1991

Image processing on a memory array architecture.

Poras T. Balsara, Mary Jane Irwin

J. VLSI Signal Process., 1991

Digit Serial Multipliers.

Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin

J. Parallel Distributed Comput., 1991

1987

Systolic & semi-systolic digit serial multipliers.

Poras T. Balsara, Robert Michael Owens

Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1986

Design and implementation of real time video processor.

Shishpal Rawat, Poras T. Balsara, Mary Jane Irwin, Tom Mackowiak

Proceedings of the IEEE International Conference on Acoustics, 1986