Poovaiah M. Palangappa

According to our database, Poovaiah M. Palangappa authored at least 10 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Graph Enhanced Feature Engineering for Privacy Preserving Recommendation Systems.

Chendi Xue, Xinyao Wang, Yu Zhou, Poovaiah M. Palangappa, Rita Brugarolas Brufau, Aasavari Dhananjay Kakne, Ravi Motwani, Ke Ding, Jian Zhang

Proceedings of the ACM RecSys Challenge 2023, Singapore, 19 September 2023, 2023

2018

Combating Bit Errors From Stuck Cells in Flash Memory Using Novel Information Theory Techniques.

Ravi Motwani, Zion S. Kwok, Poovaiah M. Palangappa

Proceedings of the 2018 International Conference on Computing, 2018

RAPID: read acceleration for improved performance and endurance in MLC/TLC NVMs.

Poovaiah M. Palangappa, Kartik Mohanram

Proceedings of the International Conference on Computer-Aided Design, 2018

CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs.

Poovaiah M. Palangappa, Kartik Mohanram

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

ECS: Error-Correcting Strings for Lifetime Improvements in Nonvolatile Memories.

Shivam Swami, Poovaiah M. Palangappa, Kartik Mohanram

ACM Trans. Archit. Code Optim., 2017

CompEx++: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVMs.

Poovaiah M. Palangappa, Kartik Mohanram

ACM Trans. Archit. Code Optim., 2017

2016

WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory.

Poovaiah M. Palangappa, Jiayin Li, Kartik Mohanram

IEEE Trans. Computers, 2016

CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM.

Poovaiah M. Palangappa, Kartik Mohanram

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories.

Poovaiah M. Palangappa, Kartik Mohanram

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Compression architecture for bit-write reduction in non-volatile memory technologies.

David B. Dgien, Poovaiah M. Palangappa, Nathan Altay Hunter, Jiayin Li, Kartik Mohanram

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014