Pong P. Chu

Orcid: 0000-0002-7241-0362

According to our database1, Pong P. Chu authored at least 11 papers between 1991 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2023
Effects of a Spiral Curriculum With Application-Based Project and Lab Components on Motivation and Achievement of Engineering Students in an Urban University.
IEEE Trans. Educ., February, 2023

2015
A cost-effective way to expand the scope of FPGA based projects.
Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

1999
Reconfigurable FPGA for Network Performance Evaluation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

1997
The impact of beam forming on the performance of an on-board output buffer.
Telecommun. Syst., 1997

1996
A Reprogrammable FPGA-Based ATM Traffic Generator.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995
Applying Neural Networks to Find the Minimum Cost Coverage of a Boolean Function.
VLSI Design, 1995

ATM burst traffic generator.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994
Neural networks as a parallel processing paradigm: potential and problems.
Neural Parallel Sci. Comput., 1994

Write Buffer Design for On-Chip Cache.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
Neural network for solving optimization problems with linear equality constraints.
Neural Parallel Sci. Comput., 1993

1991
Applying Hopfield network to find the minimum cost coverage of a Boolean function.
Proceedings of the First Great Lakes Symposium on VLSI, 1991


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