Pong-Fei Lu

According to our database1, Pong-Fei Lu authored at least 24 papers between 1992 and 2025.

Collaborative distances:

Timeline

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Links

On csauthors.net:

Bibliography

2025
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC.
IEEE J. Solid State Circuits, January, 2025

2024

2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022

2021


2020
Efficient AI System Design With Cross-Layer Approximate Computing.
Proc. IEEE, 2020


2018


2016
Gate movement for timing improvement on row based Dual-VDD designs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Synthesis design strategies for energy-efficient microprocessors.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Long-term data for BTI degradation in 32nm IBM microprocessor using HKMG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Long-term NBTI degradation under real-use conditions in IBM microprocessors.
Microelectron. Reliab., 2014

Row Based Dual-VDD Island Generation and Placement.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
On-chip circuit to monitor long-term NBTI and PBTI degradation.
Microelectron. Reliab., 2013

2012
Design of ring oscillator structures for measuring isolated NBTI and PBTI.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2006
A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

2001
A Semi-Custom Design Flow in High-Performance Microprocessor Design.
Proceedings of the 38th Design Automation Conference, 2001

1998
SOI for digital CMOS VLSI: design considerations and advances.
Proc. IEEE, 1998

1997
Floating-body effects in partially depleted SOI CMOS circuits.
IEEE J. Solid State Circuits, 1997

1996
Floating body effects in partially-depleted SOI CMOS circuits.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1993
High-speed low-power Darlington ECL circuit.
IEEE J. Solid State Circuits, December, 1993

1992
High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage.
IEEE J. Solid State Circuits, August, 1992


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