Po-Yi Huang
According to our database1,
Po-Yi Huang
authored at least 9 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2024
A 0.296pJ/bit 17.9Tb/s/mm<sup>2</sup> Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2019
A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2014
Erratum to "Application of polynomial method to on-line list colouring of graphs" [European J. Combin. 33(2012) 872-883].
Eur. J. Comb., 2014
Congruences of Finite Summations of the Coefficients in certain Generating Functions.
Electron. J. Comb., 2014
2012
Eur. J. Comb., 2012
2011
IEEE Trans. Instrum. Meas., 2011
2010