Po-Yao Chuang

According to our database, Po-Yao Chuang authored at least 12 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair.

Erik Jan Marinissen, Vineet Pancholi, Po-Yao Chuang, Martin Keim

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Test and Repair Improvements for UCIe.

Tsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen

Proceedings of the IEEE European Test Symposium, 2024

New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405.

Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra

Proceedings of the IEEE European Test Symposium, 2024

2023

Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages.

Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency.

Po-Yao Chuang, Francesco Lorenzelli, Erik Jan Marinissen

Proceedings of the IEEE International Test Conference in Asia, 2023

Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages.

Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen

Proceedings of the IEEE International 3D Systems Integration Conference, 2023

2022

A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime.

Hong-Hao Wang, Po-Yao Chuang, Cheng-Wen Wu

Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2020

A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification.

Pai-Yu Tan, Po-Yao Chuang, Yen-Ting Lin, Cheng-Wen Wu, Juin-Ming Lu

CoRR, 2020

A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.

Po-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018

Covering hard-to-detect defects by thermal quorum sensing.

Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen

Proceedings of the 23rd IEEE European Test Symposium, 2018

2017

Cell-aware test generation time reduction by using switch-level ATPG.

Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen

Proceedings of the International Test Conference in Asia, 2017

2016

Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation.

Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang, Cheng-Wen Wu

Proceedings of the 25th IEEE Asian Test Symposium, 2016