Po-Yao Chuang
Orcid: 0000-0001-7325-8836
According to our database1,
Po-Yao Chuang
authored at least 12 papers
between 2016 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2016
2017
2018
2019
2020
2021
2022
2023
2024
0
1
2
3
4
1
3
3
1
1
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
IEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Proceedings of the IEEE European Test Symposium, 2024
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405.
Proceedings of the IEEE European Test Symposium, 2024
2023
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency.
Proceedings of the IEEE International Test Conference in Asia, 2023
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages.
Proceedings of the IEEE International 3D Systems Integration Conference, 2023
2022
A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
2020
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification.
CoRR, 2020
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
2017
Proceedings of the International Test Conference in Asia, 2017
2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016