Po-Wei Chiu
Orcid: 0000-0002-4211-1564
According to our database1,
Po-Wei Chiu
authored at least 8 papers
between 2018 and 2023.
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Bibliography
2023
Proceedings of the 8th IEEE International Conference on Smart Cloud, 2023
2022
A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2021
A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2021
2020
A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer.
IEEE J. Solid State Circuits, 2018
A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018