Po-Jui Chiang

According to our database, Po-Jui Chiang authored at least 2 papers in 2019.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2019

Design of a 25-Gb/s PAM-4 VCSEL Diode Driver with an Equalizer in 90-nm CMOS Technology.

Tsung-Yen Wu, Jau-Ji Jou, Tien-Tsorng Shih, Po-Jui Chiang, Yaw-Dung Wu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Design of High-Speed Optical Receiver Module for 160Gb/s NRZ and 200Gb/s PAM4 Transmissions.

Jian-Yu Lai, Chuan-Yu Liao, Jau-Ji Jou, Tien-Tsorng Shih, Po-Jui Chiang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019