Po-Hao Wang
Orcid: 0000-0002-4598-7123
According to our database1,
Po-Hao Wang
authored at least 8 papers
between 2013 and 2017.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
2016
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors.
Integr., 2016
2015
A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation.
Proceedings of the VLSI Design, Automation and Test, 2015
2014
The reflexive printer: toward making sense of perceived drawbacks in technology-mediated reminiscence.
Proceedings of the Designing Interactive Systems Conference 2014, DIS '14, Vancouver, BC, 2014
Proceedings of the Companion Publication of the 2014 ACM SIGCHI Conference on Designing Interactive Systems Conference, 2014
2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013