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Po-Han Wang

Affiliations:
  • National Taiwan University, Department of Computer Science and Information Engineering, Taipei, Taiwan


According to our database1, Po-Han Wang authored at least 10 papers between 2009 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures.
[BibTeX]
[DOI]
Hsueh-Chun Fu
,
Po-Han Wang
,
Chia-Lin Yang
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling.
[BibTeX]
[DOI]
Li-Jhan Chen
,
Hsiang-Yun Cheng
,
Po-Han Wang
,
Chia-Lin Yang
IEEE Comput. Archit. Lett., 2017

Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.
[BibTeX]
[DOI]
Li Wang
,
Ren-Wei Tsai
,
Shao-Chung Wang
,
Kun-Chih Chen
,
Po-Han Wang
,
Hsiang-Yun Cheng
,
Yi-Chung Lee
,
Sheng-Jie Shu
,
Chun-Chieh Yang
,
Min-Yih Hsu
,
Li-Chen Kan
,
Chao-Lin Lee
,
Tzu-Chieh Yu
,
Rih-Ding Peng
,
Chia-Lin Yang
,
Yuan-Shin Hwang
,
Jenq Kuen Lee
,
Shiao-Li Tsao
,
Ming Ouhyoung
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Enabling fast preemption via Dual-Kernel support on GPUs.
[BibTeX]
[DOI]
Li-Wei Shieh
,
Kun-Chih Chen
,
Hsueh-Chun Fu
,
Po-Han Wang
,
Chia-Lin Yang
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture.
[BibTeX]
[DOI]
Po-Han Wang
,
Cheng-Hsuan Li
,
Chia-Lin Yang
Proceedings of the 53rd Annual Design Automation Conference, 2016

2014
Full system simulation framework for integrated CPU/GPU architecture.
[BibTeX]
[DOI]
Po-Han Wang
,
Gen-Hong Liu
,
Jen-Chieh Yeh
,
Tse-Min Chen
,
Hsu-Yao Huang
,
Chia-Lin Yang
,
Shih-Lien Liu
,
James Greensky
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2012
A cycle-level SIMT-GPU simulation framework.
[BibTeX]
[DOI]
Po-Han Wang
,
Chien-Wei Lo
,
Chia-Lin Yang
,
Yu-Jung Cheng
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

2011
Power gating strategies on GPUs.
[BibTeX]
[DOI]
Po-Han Wang
,
Chia-Lin Yang
,
Yen-Ming Chen
,
Yu-Jung Cheng
ACM Trans. Archit. Code Optim., 2011

2010
PM-COSYN: PE and memory co-synthesis for MPSoCs.
[BibTeX]
[DOI]
Yi-Jung Chen
,
Chia-Lin Yang
,
Po-Han Wang
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A Predictive Shutdown Technique for GPU Shader Processors.
[BibTeX]
[DOI]
Po-Han Wang
,
Yen-Ming Chen
,
Chia-Lin Yang
,
Yu-Jung Cheng
IEEE Comput. Archit. Lett., 2009


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