Po-Chun Huang
Orcid: 0000-0001-6860-6293
According to our database1,
Po-Chun Huang
authored at least 66 papers
between 2008 and 2024.
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024
Well-Posedness of the Schrödinger-Korteweg-de Vries System with Robin Boundary Conditions on the Half-Line.
Axioms, August, 2024
Axioms, 2024
PRESS: Persistence Relaxation for Efficient and Secure Data Sanitization on Zoned Namespace Storage : (Invited Paper).
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories.
ACM Trans. Embed. Comput. Syst., October, 2023
Granularity-Driven Management for Reliable and Efficient Skyrmion Racetrack Memories.
IEEE Trans. Emerg. Top. Comput., 2023
Proceedings of the International Symposium on Memory Systems, 2023
A Novel Compact Current Driver Circuit with Temperature Feedback Control for 2D Nanophotonic Phased Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
HF-Dedupe: Hierarchical Fingerprint Scheme for High Efficiency Data Deduplication on Flash-based Storage Systems.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
IEEE Trans. Computers, 2022
Proceedings of the 5th IEEE International Conference on Knowledge Innovation and Invention, 2022
2021
Making Frequent-Pattern Mining Scalable, Efficient, and Compact on Nonvolatile Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proceedings of the IEEE Virtual Reality and 3D User Interfaces, 2021
Go Gig or Go Home: Enabling Social Sensing to Share Personal Data with Intimate Partner for the Health and Wellbeing of Long-Hour workers.
Proceedings of the CHI '21: CHI Conference on Human Factors in Computing Systems, 2021
2020
IEEE Trans. Vis. Comput. Graph., 2020
Downsizing Without Downgrading: Approximated Dynamic Time Warping on Nonvolatile Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proc. ACM Hum. Comput. Interact., 2020
Proceedings of the ISWC '20: 2020 ACM International Symposium on Wearable Computers, 2020
Cross-layer Caching/Buffering Design for Search Trees based on Non-volatile Main Memories.
Proceedings of the 3rd IEEE International Conference on Knowledge Innovation and Invention, 2020
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system.
Integr., 2018
Performance optimization of heterogeneous cloud storage with bandwidth & capacity considerations.
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Downsampling of time-series data for approximated dynamic time warping on nonvolatile memories.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Space-Efficient Index Scheme for PCM-Based Multiversion Databases in Cyber-Physical Systems.
ACM Trans. Embed. Comput. Syst., 2016
Capacity-Independent Address Mapping for Flash Storage Devices with Explosively Growing Capacity.
IEEE Trans. Computers, 2016
Proceedings of the Second International Symposium on Memory Systems, 2016
Proceedings of the 45th International Conference on Parallel Processing, 2016
High-speed low-area-cost VLSI design of polar codes encoder architecture using radix-k processing engines.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016
Relay-based key management to support secure deletion for resource-constrained flash-memory storage devices.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
LEGO-based VLSI design and implementation of polar codes encoder architecture with radix-2 processing engines.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Block-Based Multi-Version B<sup>+</sup>-Tree for Flash-Based Embedded Database Systems.
IEEE Trans. Computers, 2015
IEEE Trans. Computers, 2015
Reliability-aware striping with minimized performance overheads for flash-based storage devices.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015
Proceedings of the 2015 Conference on research in adaptive and convergent systems, 2015
Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015
Proceedings of the IIAI 4th International Congress on Advanced Applied Informatics, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
IEEE J. Solid State Circuits, 2014
J. Syst. Archit., 2014
Proceedings of the International Conference on Smart Computing, 2014
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014
21.2 A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Adaptive range-based address mapping for the flash storage devices with explosive capacity.
Proceedings of the 8th International Conference on Ubiquitous Information Management and Communication, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
An index-based management scheme with adaptive caching for huge-scale low-cost embedded flash storages.
ACM Trans. Design Autom. Electr. Syst., 2013
Reliability Enhancement of Flash-Memory Storage Systems: An Efficient Version-Based Design.
IEEE Trans. Computers, 2013
Joint management of performance-predictable virtualized storage devices with hard disk and flash memory.
Proceedings of the Research in Adaptive and Convergent Systems, 2013
New ERA: new efficient reliability-aware wear leveling for endurance enhancement of flash storage devices.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
2012
A caching-oriented management design for the performance enhancement of solid-state drives.
ACM Trans. Storage, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Proceedings of the 48th Design Automation Conference, 2011
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
2010
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010
Proceedings of the 2010 Workshop on Embedded Systems Education, 2010
2009
Component-based software version management based on a Component-Interface Dependency Matrix.
J. Syst. Softw., 2009
2008
Proceedings of the 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008), 2008