Po-Ching Hsu

According to our database, Po-Ching Hsu authored at least 3 papers between 1996 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

At-Speed Logic BIST Architecture for Multi-Clock Designs.

Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

At-Speed Logic BIST for IP Cores.

B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu

Proceedings of the 2005 Design, 2005

1996

Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.

Po-Ching Hsu, Sying-Jyan Wang

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996