Po-Chih Tseng

According to our database1, Po-Chih Tseng authored at least 21 papers between 2001 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2009
Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System.
IEEE Trans. Circuits Syst. Video Technol., 2009

2007
Reconfigurable architecture for video applications.
Proceedings of the 2007 IEEE International SOC Conference, 2007

2006
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.
J. VLSI Signal Process., 2005

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization.
J. VLSI Signal Process., 2005

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.
J. VLSI Signal Process., 2005

Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform.
IEEE Trans. Signal Process., 2005

Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method.
IEEE Trans. Circuits Syst. Video Technol., 2005

Advances in Hardware Architectures for Image and Video Coding - A Survey.
Proc. IEEE, 2005

Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Nearly Lossless Content-Dependent Low-Power DCT Design for Mobile Video Applications.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

2004
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
IEEE Trans. Signal Process., 2004

Reconfigurable discrete cosine transform processor for object-based video signal processing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low-power parallel tree architecture for full search block-matching motion estimation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

B-spline factorization-based architecture for inverse discrete wavelet transform.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Memory analysis and architecture for two-dimensional discrete wavelet transform.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank.
Proceedings of the 2003 International Conference on Image Processing, 2003

2002
VLSI implementation of shape-adaptive discrete wavelet transform.
Proceedings of the Visual Communications and Image Processing 2002, 2002

Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
CDSP: an application-specific digital signal processor for third generation wireless communications.
IEEE Trans. Consumer Electron., 2001


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