Po-Chang Tsai

According to our database, Po-Chang Tsai authored at least 4 papers between 2005 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction.

Po-Chang Tsai, Sying-Jyan Wang

IET Comput. Digit. Tech., 2008

2007

Test Data Compression for Minimum Test Application Time.

Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh

J. Inf. Sci. Eng., 2007

Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture.

Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li

Proceedings of the 16th Asian Test Symposium, 2007

2005

FSM-based programmable memory BIST with macro command.

Po-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005