Plamen Asenov
According to our database1,
Plamen Asenov
authored at least 9 papers
between 2011 and 2024.
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2024
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Bibliography
2024
Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Modeling and Simulation for DRAM and Flash Memory Technology Exploration and Development.
Proceedings of the IEEE International Memory Workshop, 2024
2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
2015
Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2013
Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models.
Proceedings of 2013 International Conference on IC Design & Technology, 2013
2012
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2011