Piotr Patronik
Orcid: 0000-0002-8647-1705
According to our database1,
Piotr Patronik
authored at least 16 papers
between 2005 and 2023.
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Bibliography
2023
Design of reverse converters for the general RNS 3-moduli set {2<sup>k</sup>, 2<sup>n</sup> - 1, 2<sup>n</sup> + 1}.
EURASIP J. Adv. Signal Process., December, 2023
2020
2018
Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels.
J. Signal Process. Syst., 2018
Correction to: Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2<sup>k</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>n+1</sup>-1, 2<sup>n-1</sup>-1} (<i>n</i> Even).
Circuits Syst. Signal Process., 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2<sup>k</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>n+1</sup>-1, 2<sup>n-1</sup>-1} (<i>n</i> Even).
Circuits Syst. Signal Process., 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
2015
Proceedings of the Nordic Circuits and Systems Conference, 2015
2014
Design of Reverse Converters for the New RNS Moduli Set {2<sup>n</sup>+1, 2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n-1</sup>+1} (<i>n</i> odd).
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Design of Reverse Converters for General RNS Moduli Sets {2<sup>k</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>n+1</sup>-1} and {2<sup>k</sup>, 2<sup>n</sup>-1, 2<sup>n</sup>+1, 2<sup>n-1</sup>-1} (n even).
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Fast and accurate thermal modeling and simulation of manycore processors and workloads.
Microelectron. J., 2013
2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
2011
Fast and energy-efficient constant-coefficient FIR filters using residue number system.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
2005
Delay Testability Properties of Circuits Implementing Threshold and Symmetric Functions.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005