Ping-Ying Wang

According to our database, Ping-Ying Wang authored at least 14 papers between 2005 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter.

Che-Fu Liang, Ping-Ying Wang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 1V fractional-N PLL with nonlinearity-insensitive modulator.

Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO.

Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits.

Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011

An all-digital built-in self-test technique for transfer function characterization of RF PLLs.

Ping-Ying Wang, Hsiu-Ming Chang, Kwang-Ting Cheng

Proceedings of the Design, Automation and Test in Europe, 2011

2010

All digital modulation bandwidth extension technique for narrow bandwidth analog fractional-N PLL.

Ping-Ying Wang, Chia-Huang Fu

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes.

Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Hsiu-Ming (Sherman) Chang

IEEE J. Solid State Circuits, 2009

2008

A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE.

Hsiang-Hui Chang, Ping-Ying Wang, Jing-Hong Conan Zhan, Bing-Yu Hsieh

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A charge pump-based direct frequency modulator.

Ping-Ying Wang, Hsiu-Ming Chang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A fractional spur reduction technique for RF TDC-based all digital PLLs.

Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan

Proceedings of the ESSCIRC 2008, 2008

An analog enhanced all digtial RF fractional-N PLL with self-calibrated capability.

Ping-Ying Wang, Jing-Hong Conan Zhan, Hsiang-Hui Chang, Bing-Yu Hsieh

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction.

Ping-Ying Wang, Meng-Ta Yang, Shang-Ping Chen, Meng-Hsueh Lin, Jing-Bing Yang

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

Chaos in delay locked loop.

Ping-Ying Wang, C.-H. Chou, Hsueh-Wu Kao

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A phase locked loop with a mixed mode loop filter for clock/data recovery in optical disc drives.

Ping-Ying Wang, Hsiang Ji Hsieh, Yung-Yu Lin, Meng-Ta Yang, Hsueh-Wu Kao

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005