Ping-Hung Yuh

According to our database1, Ping-Hung Yuh authored at least 20 papers between 2004 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Accurate 3-D capacitance extractions for advanced nanometer CMOS nodes.
Proceedings of the VLSI Design, Automation and Test, 2015

2012
Optimized 3D Network-on-Chip Design Using Simulated Allocation.
ACM Trans. Design Autom. Electr. Syst., 2012

2011
A SAT-based routing algorithm for cross-referencing biochips.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

2010
Application-specific 3D Network-on-Chip design using simulated allocation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2009

T-trees: A tree-based representation for temporal and three-dimensional floorplanning.
ACM Trans. Design Autom. Electr. Syst., 2009

A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A progressive-ILP based routing algorithm for cross-referencing biochips.
Proceedings of the 45th Design Automation Conference, 2008

2007
Temporal floorplanning using the three-dimensional transitive closure subGraph.
ACM Trans. Design Autom. Electr. Syst., 2007

Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation.
ACM J. Emerg. Technol. Comput. Syst., 2007

Post-placement leakage optimization for partially dynamically reconfigurable FPGAs.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

BioRoute: a network-flow based routing algorithm for digital microfluidic biochips.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs.
Proceedings of the 44th Design Automation Conference, 2007

2006
Placement of digital microfluidic biochips using the t-tree formulation.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Joint exploration of architectural and physical design spaces with thermal consideration.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A routing algorithm for flip-chip design.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
Temporal floorplanning using the T-tree formulation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Temporal floorplanning using 3D-subTCG.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004


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