Ping Gui

Orcid: 0000-0002-3197-4903

According to our database1, Ping Gui authored at least 54 papers between 2005 and 2024.

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Bibliography

2024
A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS.
IEEE Access, 2024

Controller Area Network (CAN) Bus Transceiver with Enhanced Rail Converter.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023
Coordinating an emergency medical material supply chain with CVaR under the pandemic considering corporate social responsibility.
Comput. Ind. Eng., February, 2023

Research on the path choice behavior of donated materials under major epidemics.
Kybernetes, 2023

2022
A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoM<sub>S</sub> in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A 12-Bit 1 GS/s RF Sampling Pipeline-SAR ADC With Harmonic Injecting Cross-Coupled Pair Achieving 7.5 fj/Conv-Step.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Analyzing a community worker's stress during the COVID-19 pandemic in China.
Kybernetes, 2022

A Low-Noise Low-Power Chopper Instrumentation Amplifier With Robust Technique for Mitigating Chopping Ripples.
IEEE J. Solid State Circuits, 2022

Controller Area Network (CAN) Bus Transceiver with Authentication Support.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations.
IEEE Trans. Emerg. Top. Comput., 2021

A 76-81-GHz Four-Channel Digitally Controlled CMOS Receiver for Automotive Radars.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design and Characterization of a 10-MHz GaN Gate Driver Using On-Chip Feed-Forward Gaussian Switching Regulation for EMI Reduction.
IEEE J. Solid State Circuits, 2021

A General-Regression-Neural-Network Based 5V-to-48V Three-Level Buck/Boost Power Converter with 40dB PSRR 90%-Efficiency for SSD Power Loss Protection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

A 1GS/s 82dB Peak-SFDR 12b Single-Channel Pipe-SAR ADC with Harmonic-Injecting Cross-Coupled-Pair and Fast N-replica Bootstrap Switch Achieving 7.5fj/conv-step.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Hybrid Line Driver with Voltage-Mode SST Pre-Emphasis and Current-Mode Equalization.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 13nV/✓Hz 4.5μW Chopper Instrumentation Amplifier with Robust Ripple Reduction and Input Impedance Boosting Techniques.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Early-warning analysis of crowd stampede in metro station commercial area based on internet of things.
Multim. Tools Appl., 2019

IoT-based real time intelligent routing for emergent crowd evacuation.
Libr. Hi Tech, 2019

85-110-GHz CMOS Magnetic-Free Nonreciprocal Components for Full-Duplex Transceivers.
IEEE J. Solid State Circuits, 2019

A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019

Compact and high-linearity 77 GHz CMOS receiver front-end for automotive radar.
IET Circuits Devices Syst., 2019

Innovate Practices on CyberSecurity of Hardware Semiconductor Devices.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Digitally Controlled CMOS Receiver with -14 dBm P1dB for 77 GHz Automotive Radar.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 76-81 GHz CMOS PA with 16-dBm PSAT and 30-dB Amplitude Control for MIMO Automotive Radars.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 14nV/√Hz 14μW Chopper Instrumentation Amplifier with Dynamic Offset Zeroing (DOZ) Technique for Ripple Reduction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A Low-Voltage Low-Phase-Noise 25-GHz Two-Tank Transformer-Feedback VCO.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Real-time monitoring of test fallout data to quickly identify tester and yield issues in a multi-site environment.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

A 31.5-GHz BW 6.4-b ENOB 56-GS/s ADC in 28nm CMOS for 224-Gb/s DP-16QAM coherent receivers.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Temperature Compensated Triple-Path PLL With K<sub>VCO</sub> Non-Linearity Desensitization Capable of Operating at 77 K.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Detecting a trojan die in 3D stacked integrated circuits.
Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

A 43.6-dB SNDR 1-GS/s single-channel SAR ADC using coarse and fine comparators with background comparator offset calibration.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Wireless Networking Testbed and Emulator (WiNeTestEr).
Comput. Commun., 2016

Using Existing Reconfigurable Logic in 3D Die Stacks for Test.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

2015
Effect of OPAMP Input Offset on Continuous-Time ΔΣ Modulators With Current-Mode DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 180-V<sub>pp</sub> Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

An Industrial Case Study: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices.
Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2014
An Integrated High-Voltage Low-Distortion Current-Feedback Linear Power Amplifier for Ultrasound Transmitters Using Digital Predistortion and Dynamic Current Biasing Techniques.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A low-power 28 Gb/s CDR using artificial lc transmission line technique in 65 nm CMOS.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Wireless networking testbed and emulator (WiNeTestEr).
Proceedings of the 17th ACM International Conference on Modeling, 2014

54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2012
A current-steering DAC-based CMOS ultra-wideband transmitter with bi-phase modulation.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2010
Analysis of Harmonic Energy Distribution Portfolio for Digital-to-Frequency Converters.
IEEE Trans. Instrum. Meas., 2010

The Effects of Flying-Adder Clocks on Digital-to-Analog Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A comparative study between Fractional-N PLL and Flying-Adder PLL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 250MHz-to-4GHz Δ-Σ fractional-N frequency synthesizer with adjustable duty cycle.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Simulation Study of Time-Average-Frequency based Clock Signal Driving Systems with Embedded Digital-to-Analog Converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Wide-tuning-range and Reduced-fractional-spurs Synthesizer Combining Sigma-Delta Fractional-N and Integer Flying-Adder Techniques.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2005
A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC.
IEEE Trans. Very Large Scale Integr. Syst., 2005


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