Ping-Chuan Chiang
Orcid: 0000-0002-2004-9413
According to our database1,
Ping-Chuan Chiang
authored at least 12 papers
between 2011 and 2020.
Collaborative distances:
Collaborative distances:
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On csauthors.net:
Bibliography
2020
IEEE J. Solid State Circuits, 2020
Proceedings of the European Conference on Optical Communications, 2020
2019
A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
IEEE J. Solid State Circuits, 2017
2015
IEEE J. Solid State Circuits, 2015
4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2011
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension.
Proceedings of the International SoC Design Conference, 2011