Pinalkumar Engineer
Orcid: 0000-0002-4955-232X
According to our database1,
Pinalkumar Engineer
authored at least 8 papers
between 2012 and 2024.
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Bibliography
2024
FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing.
J. Circuits Syst. Comput., September, 2024
2023
Parallelizing Non-Neural ML Algorithm for Edge-based Face Recognition on Parallel Ultra-Low Power (PULP) Cluster.
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023
Memory-efficient Edge-based Non-Neural Face Recognition Algorithm on the Parallel Ultra-Low Power (PULP) Cluster.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
2020
Scalable implementation of particle filter-based visual object tracking on network-on-chip (NoC).
J. Real Time Image Process., 2020
2015
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.
CoRR, 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
2012
Proceedings of the International Symposium on Electronic System Design, 2012