Pin-En Su

According to our database, Pin-En Su authored at least 10 papers between 2009 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

IEEE J. Solid State Circuits, 2017

2016

A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.

Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Kun Tan, Aravind Padyana, Vincent Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Bryan Juo-Jung Hung, Massimo Brandolini, Maco Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young J. Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hanson Hung-Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Ray Gomez

IEEE J. Solid State Circuits, 2016

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.

Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver.

Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Tan, Aravind Padyana, Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Juo-Jung Hung, Massimo Brandolini, Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hung Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Gomez

Proceedings of the Symposium on VLSI Circuits, 2015

2011

A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation.

Pin-En Su, Sudhakar Pamarti

IEEE J. Solid State Circuits, 2011

Open-Loop Wide-Bandwidth Phase Modulation Techniques.

Nitin Nidhi, Pin-En Su, Sudhakar Pamarti

J. Electr. Comput. Eng., 2011

2010

Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-N PLLs.

Pin-En Su, Sudhakar Pamarti

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 3 , ˟, 3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation.

Tzu-Chien Hsueh, Pin-En Su, Sudhakar Pamarti

IEEE J. Solid State Circuits, 2010

2009

Fractional-N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial.

Pin-En Su, Sudhakar Pamarti

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 3×3.8Gb/s four-wire high speed I/O link based on CDMA-like crosstalk cancellation.

Tzu-Chien Hsueh, Pin-En Su, Sudhakar Pamarti

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009