Pil-Ho Lee
Orcid: 0000-0002-8096-8518
According to our database1,
Pil-Ho Lee
authored at least 13 papers
between 2014 and 2022.
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Bibliography
2022
A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022
2021
Proceedings of the 18th International SoC Design Conference, 2021
2020
A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization.
IEEE Trans. Circuits Syst., 2020
2019
IEEE Trans. Consumer Electron., 2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
2017
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2.
IEEE Trans. Consumer Electron., 2017
A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display.
IEICE Trans. Electron., 2017
Proceedings of the International SoC Design Conference, 2017
0.5 kHz-32 MHz digital fractional-N frequency synthesizer with burst-frequency switch.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators.
IEICE Trans. Electron., 2016
An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis.
IEICE Trans. Electron., 2016
2014
A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle.
IEICE Trans. Electron., 2014