Pietro Andreani

Orcid: 0000-0001-9640-9908

According to our database1, Pietro Andreani authored at least 106 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2018, "For contributions to CMOS integrated voltage-controlled oscillators".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS.
IEEE Access, 2024

Asynchronous vs Synchronous SAR ADCs - Performance Beyond Nominal Speed.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024

2023
On the Calculation and Simulation of Loop Gain in Feedback Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023

Some Results on Oscillation Stability in Multi-Mode Harmonic Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOS.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

A Technique to Increase the Linearity of the Bootstrapped Switch.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

A High-Speed Comparator Using a New Regeneration Latch.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise.
IEEE J. Solid State Circuits, 2022

2020
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO.
IEEE J. Solid State Circuits, 2020

A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects.
IEEE J. Solid State Circuits, 2020

A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020

A 10-Bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
An Accurate Analysis of Phase Noise in CMOS Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 5 GHz CT $\Delta\sum$ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
On the Remarkable Performance of the Series-Resonance CMOS Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
A General Theory of Phase Noise in Transconductor-Based Harmonic Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
Still More on the 1/f<sup>2</sup> Phase Noise Performance of Harmonic Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 65 nm CMOS Wideband Radio Receiver With ΔΣ-Based A/D-Converting Channel-Select Filters.
IEEE J. Solid State Circuits, 2016

New Associate Editors.
IEEE J. Solid State Circuits, 2016

An experimental comparison between two widely adopted phase noise models.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

2015
Digital background calibration in continuous-time delta-sigma analog to digital converters.
Proceedings of the Nordic Circuits and Systems Conference, 2015

A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise.
Proceedings of the Nordic Circuits and Systems Conference, 2015

A 0.6-3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers.
IEEE J. Solid State Circuits, 2014

A Filtering ΔΣ ADC for LTE and Beyond.
IEEE J. Solid State Circuits, 2014

A low-power 2nd-order CT ΔΣ modulator with an asynchronous SAR quantizer.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

21.6 A 2.4-to-5.3GHz dual-core CMOS VCO with concentric 8-shaped coils.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 1-1 MASH 2-D vernier time-to-digital converter with 2<sup>nd</sup>-order noise shaping.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An 11mW continuous time delta-Sigma modulator with 20 MHz bandwidth in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Lessons from ten years of the international master's program in System-on-Chip.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

A Class-D CMOS DCO with an on-chip LDO.
Proceedings of the ESSCIRC 2014, 2014

2013
A Push-Pull Class-C CMOS VCO.
IEEE J. Solid State Circuits, 2013

Class-D CMOS Oscillators.
IEEE J. Solid State Circuits, 2013

Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs.
IEEE J. Solid State Circuits, 2013

A low-power 2nd-order CT ΔΣ modulator with a single operational amplifier.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

A 2.5-to-3.3GHz CMOS Class-D VCO.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A high-swing complementary class-C VCO.
Proceedings of the ESSCIRC 2013, 2013

A 9MHz filtering ADC with additional 2<sup>nd</sup>-order ΔΣ modulator noise suppression.
Proceedings of the ESSCIRC 2013, 2013

2012
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps.
IEEE J. Solid State Circuits, 2012

A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Low-phase-noise 3.4-4.5 GHz dynamic-bias class-C CMOS VCOs with a FoM of 191 dBc/Hz.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A TX VCO for WCDMA/EDGE in 90 nm RF CMOS.
IEEE J. Solid State Circuits, 2011

A digital PLL with a multi-delay coarse-fine TDC.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Single-ended low noise multiband LNA with programmable integrated matching and high isolation switches.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A mixed mode design flow for multi GHz ADPLLs.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Highly linear direct conversion receiver using customized on-chip balun.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Dynamic bias schemes for class-C VCOs.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011


On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Impact of MOS threshold-voltage mismatch in current-steering DACs for CT ΣΔ modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A transmitter CMOS VCO for WCDMA/EDGE.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A Time-Variant Analysis of Fundamental 1/f<sup>3</sup> Phase Noise in CMOS Parallel LC -Tank Quadrature Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A compact CMOS MEMS microphone with 66dB SNR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise.
IEEE J. Solid State Circuits, 2008

Sensitivity Degradation in a Tri-Band GSM BiCMOS Direct-Conversion Receiver Caused by Transient Substrate Heating.
IEEE J. Solid State Circuits, 2008

Author's Response.
IEEE J. Solid State Circuits, 2008

Comments on "Comments on "A General Theory of Phase Noise in Electrical Oscillators"".
IEEE J. Solid State Circuits, 2008

A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
An Analysis of 1/f<sup>2</sup> Phase Noise in Bipolar Colpitts Oscillators (With a Digression on Bipolar Differential-Pair LC Oscillators).
IEEE J. Solid State Circuits, 2007

45% Power Saving in a 0.25μm BiCMOS 10Gb/s 50Ω-Terminated Packaged Active-Load Laser Driver.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A 0.35μm 50V CMOS sliding-mode control IC for buck converters.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006
A time-variant analysis of the 1/f<sup>2</sup> phase noise in CMOS parallel LC-tank quadrature oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

On the amplitude and phase errors of quadrature LC-tank CMOS oscillators.
IEEE J. Solid State Circuits, 2006

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell.
IEEE J. Solid State Circuits, 2006

More on the$1/{\rm f}^{2}$Phase Noise Performance of CMOS Differential-PairLC-Tank Oscillators.
IEEE J. Solid State Circuits, 2006

A 240W Monolithic Class-D Audio Amplifier Output Stage.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Detailed Behavioral Modeling of Bang-Bang Phase Detectors.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A study of phase noise in colpitts and LC-tank CMOS oscillators.
IEEE J. Solid State Circuits, 2005

Technology scaling impact on embedded ADC design for telecom receivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Phase noise analysis and design of a 3-GHz bipolar differential colpitts VCO.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
On the phase-noise and phase-error performances of multiphase LC CMOS VCOs.
IEEE J. Solid State Circuits, 2004

Comparison of the image rejection between the passive and the Gilbert mixer.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Highly functional tunnelling devices integrated in 3D.
Int. J. Circuit Theory Appl., 2003

Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Tail current noise suppression in RF CMOS VCOs.
IEEE J. Solid State Circuits, 2002

On the use of Nauta's transconductor in low-frequency CMOS g<sub>m</sub>-C bandpass filters.
IEEE J. Solid State Circuits, 2002

Analysis and design of a 1.8-GHz CMOS LC quadrature VCO.
IEEE J. Solid State Circuits, 2002

Circuits and devices with integrated VFETs and RTDs.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Bandwidth considerations for a CALLUM transmitter architecture.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A 57-dB image band rejection CMOS G<sub>m</sub>-C polyphase filter with automatic frequency tuning for Bluetooth.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A 2.2 GHz CMOS VCO with inductive degeneration noise suppression.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
On the use of MOS varactors in RF VCOs.
IEEE J. Solid State Circuits, 2000

A 1.8-GHz CMOS VCO tuned by an accumulation-mode MOS varactor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A CMOS g<sub>m</sub>-C IF filter for Bluetooth.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A 2.4-GHz CMOS monolithic VCO based on an MOS varactor.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Multihit multichannel time-to-digital converter with ±1% differential nonlinearity and near optimal time resolution.
IEEE J. Solid State Circuits, 1998

Characteristic polynomial and zero polynomial with the Cochrun-Grabel method.
Int. J. Circuit Theory Appl., 1998

1993
A GSM speech coder implemented on a customized processor architecture.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


  Loading...