Pietro Andreani
Orcid: 0000-0001-9640-9908
According to our database1,
Pietro Andreani
authored at least 106 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2018, "For contributions to CMOS integrated voltage-controlled oscillators".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS.
IEEE Access, 2024
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
2022
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise.
IEEE J. Solid State Circuits, 2022
2020
IEEE J. Solid State Circuits, 2020
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects.
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 65 nm CMOS Wideband Radio Receiver With ΔΣ-Based A/D-Converting Channel-Select Filters.
IEEE J. Solid State Circuits, 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
2015
Digital background calibration in continuous-time delta-sigma analog to digital converters.
Proceedings of the Nordic Circuits and Systems Conference, 2015
Proceedings of the Nordic Circuits and Systems Conference, 2015
A 0.6-3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 1-1 MASH 2-D vernier time-to-digital converter with 2<sup>nd</sup>-order noise shaping.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
2013
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A wide bandwidth fractional-N synthesizer for LTE with phase noise cancellation using a hybrid-ΔΣ-DAC and charge re-timing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 9MHz filtering ADC with additional 2<sup>nd</sup>-order ΔΣ modulator noise suppression.
Proceedings of the ESSCIRC 2013, 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps.
IEEE J. Solid State Circuits, 2012
A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Single-ended low noise multiband LNA with programmable integrated matching and high isolation switches.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Impact of MOS threshold-voltage mismatch in current-steering DACs for CT ΣΔ modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
A Time-Variant Analysis of Fundamental 1/f<sup>3</sup> Phase Noise in CMOS Parallel LC -Tank Quadrature Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
IEEE J. Solid State Circuits, 2008
Sensitivity Degradation in a Tri-Band GSM BiCMOS Direct-Conversion Receiver Caused by Transient Substrate Heating.
IEEE J. Solid State Circuits, 2008
Comments on "Comments on "A General Theory of Phase Noise in Electrical Oscillators"".
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
An Analysis of 1/f<sup>2</sup> Phase Noise in Bipolar Colpitts Oscillators (With a Digression on Bipolar Differential-Pair LC Oscillators).
IEEE J. Solid State Circuits, 2007
45% Power Saving in a 0.25μm BiCMOS 10Gb/s 50Ω-Terminated Packaged Active-Load Laser Driver.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
A time-variant analysis of the 1/f<sup>2</sup> phase noise in CMOS parallel LC-tank quadrature oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE J. Solid State Circuits, 2006
IEEE J. Solid State Circuits, 2006
More on the$1/{\rm f}^{2}$Phase Noise Performance of CMOS Differential-PairLC-Tank Oscillators.
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE J. Solid State Circuits, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
IEEE J. Solid State Circuits, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Int. J. Circuit Theory Appl., 2003
Impact of mutual inductance and parasitic capacitance on the phase-error performance of CMOS quadrature VCOs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
On the use of Nauta's transconductor in low-frequency CMOS g<sub>m</sub>-C bandpass filters.
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
A 57-dB image band rejection CMOS G<sub>m</sub>-C polyphase filter with automatic frequency tuning for Bluetooth.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1998
Multihit multichannel time-to-digital converter with ±1% differential nonlinearity and near optimal time resolution.
IEEE J. Solid State Circuits, 1998
Int. J. Circuit Theory Appl., 1998
1993
A GSM speech coder implemented on a customized processor architecture.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993