Pieter Weckx
Orcid: 0000-0003-4579-0571
According to our database1,
Pieter Weckx
authored at least 65 papers
between 2012 and 2024.
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Bibliography
2024
Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Possible Origins, Identification, and Screening of Silent Data Corruption in Data Centers.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Proceedings of the IEEE European Test Symposium, 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs).
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper.
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022
Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proactive Run-Time Mitigation for Time-Critical Applications Using Dynamic Scenario Methodology.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
2020
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS).
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020
2019
Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Microelectron. Reliab., 2018
A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability.
Microelectron. Reliab., 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
Proceedings of the 48th European Solid-State Device Research Conference, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the International Conference on IC Design and Technology, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the 10th International Design & Test Symposium, 2015
Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technology.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulations.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
The defect-centric perspective of device and circuit reliability - From individual defects to circuits.
Proceedings of the 45th European Solid State Device Research Conference, 2015
Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow.
Proceedings of the 45th European Solid State Device Research Conference, 2015
Proceedings of the 45th European Solid State Device Research Conference, 2015
Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs.
Proceedings of the 15th Latin American Test Workshop, 2014
Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.
Microprocess. Microsystems, 2013
2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012