Pieter Schuddinck

According to our database, Pieter Schuddinck authored at least 13 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.

S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters.

Bjorn Vermeersch, Erik Bury, Yang Xiang, Pieter Schuddinck, Krishna K. Bhuwalka, Geert Hellings, Julien Ryckaert

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch.

Pieter Schuddinck, Fabian M. Bufler, Yang Xiang, Anita Farokhnejad, Gioele Mirabelli, Anne Vandooren, Bilal Chehab, A. Gupta, César Roda Neve, Geert Hellings, Julien Ryckaert

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.

Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Design enablement of CFET devices for sub-2nm CMOS nodes.

Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2017

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7.

Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.

Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016

5nm: Has the time for a device change come?

Praveen Raghavan, Marie Garcia Bardon, Peter Debacker, P. Schuddinck, Doyoung Jang, Rogier Baert, Diederik Verkest, Aaron Voon-Yew Thean

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Memories for NTC.

Tobias Gemmeke, Mohamed M. Sabry, Jan Stuijt, Pieter Schuddinck, Praveen Raghavan, Francky Catthoor

Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016

2015

Lateral NWFET optimization for beyond 7nm nodes.

Dmitry Yakimets, Doyoung Jang, Praveen Raghavan, Geert Eneman, Hans Mertens, P. Schuddinck, Arindam Mallik, Marie Garcia Bardon, Nadine Collaert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Kristin De Meyer

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling.

Marie Garcia Bardon, P. Schuddinck, Praveen Raghavan, Doyoung Jang, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Thean

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Holisitic device exploration for 7nm node.

Praveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert, Anda Mocuta, Dan Mocuta, Zsolt Tokei, Diederik Verkest, Aaron Thean, An Steegen

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Design Technology co-optimization for N10.

Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, Philippe Leray, Tsung-Te Liu, Kenichi Miyaguchi, Bertrand Parvais, Pieter Schuddinck, Philippe Weemaes, Abdelkarim Mercha, Jürgen Bömmels, Naoto Horiguchi, Greg McIntyre, Aaron Thean, Zsolt Tökei, Shaunee Cheng, Diederik Verkest, An Steegen

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014