Pieter Rombouts

Orcid: 0000-0002-3731-9731

According to our database1, Pieter Rombouts authored at least 81 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Multi-GHz Inverter-Based ASDM With Distortion Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2024

A Double-Edge Triggered Asynchronous Gray Counter for Use as a Coarse Counter in VCO ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024

Origin of Frequency-Dependent Distortion and Calibration for Ring Oscillator VCO ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024

A 3.5 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping.
CoRR, 2024

2023
The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

A Different View of Sigma-Delta Modulators Under the Lens of Pulse Frequency Modulation.
CoRR, 2023

Analysis of in-band Spurious Tones of VCO-based Analog Filters and Mitigation Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Methodology for Readout and Ring Oscillator Optimization Toward Energy-Efficient VCO-Based ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 2 MS/s Full Bandwidth Hall System with Low Offset Enabled by Randomized Spinning.
Sensors, 2022

Noise Optimization of a Resistively-Driven Ring Oscillator for VCO-Based ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Fast Offset Reduction Loop Based on a Bilinear Integrator for Sensor Readout Circuits.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

First-order Hold DAC Reconstruction Filtering for Efficient Image Rejection.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

The Analog Behavior of Pseudo Digital Ring Oscillators Used in VCO ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020
Efficient Offline Outer/Inner DAC Mismatch Calibration in Wideband ΔΣ ADCs.
IEEE Trans. Circuits Syst., 2020

2019
Low-Pass Filtering SC-DAC for Reduced Jitter and Slewing Requirements on CTSDMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Current-Mode Floating-Bridge Technique for Closed-Loop ΣΔ Readout of Wheatstone Bridge Sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

VCO-ADCs with a Quadrature Band-Pass Noise-Transfer-Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Pulse Frequency Modulation Interpretation of VCOs Enabling VCO-ADC Architectures With Extended Noise Shaping.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 1.8-pJ/b, 12.5-25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit.
IEEE J. Solid State Circuits, 2018

Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Why and How VCO-based ADCs can improve instrumentation applications.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Passive Loop Filter Assistance for CTSDMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Mostly Digital VCO-Based CT-SDM With Third-Order Noise Shaping.
IEEE J. Solid State Circuits, 2017

A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst Mode Applications in PONs.
Proceedings of the European Conference on Optical Communication, 2017

2016
Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015
Influence of Jitter on Limit Cycles in Bang-Bang Clock and Data Recovery Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014
Improved offline calibration for DAC mismatch in low OSR ΣΔ ADCs with distributed feedback.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Analyzing distortion in ASDMs with loop delay.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A Describing Function Study of Saturated Quantization and Its Application to the Stability Analysis of Multi-Bit Sigma Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Calibration of DAC Mismatch Errors in ΣΔ ADCs Based on a Sine-Wave Measurement.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Analytical Expressions for the Distortion of Asynchronous Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A double-sampling cross noise-coupled Sigma Delta modulator with a reduced amount of opamps.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Analysis of VCO based noise shaping ADCs linearized by PWM modulation.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Validation of Symbolic Expressions in Circuit Analysis E-Learning.
IEEE Trans. Educ., 2011

A Rigorous Approach to the Robust Design of Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 5-MHz 11-Bit Self-Oscillating Sigma Delta Modulator With a Delay-Based Phase Shifter in 0.025 mm <sup>2</sup>.
IEEE J. Solid State Circuits, 2011

A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time SigmaDelta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Comments on "Performance Analysis of a Hybrid Incremental and Cyclic A/D Conversion Principle".
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS.
IEEE J. Solid State Circuits, 2010

A 14-bit 250MS/s digital to analog converter with binary weighted Redundant Signed Digit coding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025mm<sup>2</sup>.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Web-Based Trainer for Electrical Circuit Analysis.
IEEE Trans. Educ., 2009

Nyquist-criterion based design of a CT SigmaDelta-ADC with a reduced number of comparators.
Integr., 2009

A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Design of an integrated analog controller for a class-D audio amplifier.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A double-sampling cross noise-coupled split ΣΔ-modulation A/D converter with 80 dB SNR.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
An Unconstrained Architecture for Systematic Design of Higher Order SigmaDelta Force-Feedback Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

An On-Line Calibration Technique for Mismatch Errors in High-Speed DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

An anti-aliasing filter inspired by continuous-time ΔΣ modulation.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Redundant signed digit coding in binary weighted DACs.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Mismatch Insensitive Double-Sampling Quadrature Bandpass SigmaDelta Modulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Efficient Multibit Quantization in Continuous-Time Sigma Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A delay-based complex double-sampled resonator for use in ƒ<i><sub>s</sub></i>/4 quadrature bandpass ΣΔ modulators.
IEICE Electron. Express, 2007

Quadrature Mismatch Shaping Techniques for Fully Differential Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An Unconstrained Architecture for High-Order Sigma Delta Force-Feedback Inertial Sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Quadrature Mismatch Shaping for Digital-to-Analog Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A simple on-chip repetitive sampling setup for the quantification of substrate noise.
IEEE J. Solid State Circuits, 2006

Quadrature mismatch shaping with a complex, tree structured DAC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Nyquist criterion based design of continuous time Sigma Delta modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A continuous-time band-pass Sigma Delta modulator implemented in 0.35µm BiCMOS using transmission lines.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Quadrature Mismatch Shaping with a Complex, Data Directed Swapper.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Design of double-sampling ΣΔ modulation A/D converters with bilinear integrators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A versatile Nyquist-rate A/D converter with 16-18 bit performance for sensor readout applications.
Integr., 2005

Synthesis of sigma delta modulators employing continuous time delays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

STF behaviour in a CT ΔΣ modulator.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2004
Systematic design of double-sampling ΣΔ A/D converters with a modified noise transfer function.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A double-sampling extended-counting ADC.
IEEE J. Solid State Circuits, 2004

Systematic design of double-sampling Sigma Delta ADC's with modified NTF.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Addressing static and dynamic errors in bandpass unit element multibit DAC's.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A jitter insensitive continuous-time ΣΔ modulator using transmission lines.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003
An approach to tackle quantization noise folding in double-sampling ΣΔ modulation A/D converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

A 250-kHz 94-dB double-sampling ΣΔ modulation A/D converter with a modified noise transfer function.
IEEE J. Solid State Circuits, 2003

2002
An efficient technique to eliminate quantisation noise folding in double-sampling Sigma-Delta modulators.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
A 13.5-b 1.2-V micropower extended counting A/D converter.
IEEE J. Solid State Circuits, 2001

1998
Dynamic element matching for pipelined A/D conversion.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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