Piet Engelke

According to our database, Piet Engelke authored at least 35 papers between 2000 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

IJTAG Through a Two-Pin Chip Interface.

Manu Baby, Bernd Büttner, Piet Engelke, Ulrike Pfannkuchen, Reinhard Meier, Jonathan Gaudet, Jean-François Côté, Givargis Danialy, Martin Keim, Lori Schramm

Proceedings of the IEEE International Test Conference, 2020

2017

BASTION: Board and SoC test instrumentation for ageing and no failure found.

Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2014

Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures.

Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Glaß, Felix Reimann, Laura Rodríguez Gómez, Thomas Russ, Jürgen Teich, Dominik Ull, Hans-Joachim Wunderlich

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures.

Felix Reimann, Michael Glaß, Jürgen Teich, Alejandro Cook, Laura Rodríguez Gómez, Dominik Ull, Hans-Joachim Wunderlich, Piet Engelke, Ulrich Abelein

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Struktureller Test im System.

Piet Engelke

Proceedings of the Aspekte der Technischen Informatik, 2014

2013

On the feasibility of combining on-line-test and self repair for logic circuits.

Tobias Koal, Markus Ulbricht, Piet Engelke, Heinrich Theodor Vierhaus

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

Funding project DIANA - Integrated diagnostics for the analysis of electronic failures in vehicles.

Piet Engelke, Hermann Obermeir

Proceedings of the 17th IEEE European Test Symposium, 2012

Scan Based Tests via Standard Interfaces.

Christian Gleichner, Heinrich Theodor Vierhaus, Piet Engelke

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2010

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis.

Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker

Int. J. Parallel Program., 2010

2009

Resistive bridging faults - defect-oriented modeling and efficient testing (Resistive bridging faults - defektorientierte Modellierung und effizienter Test)

Piet Engelke

PhD thesis, 2009

SUPERB: Simulator utilizing parallel evaluation of resistive bridges.

Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian

ACM Trans. Design Autom. Electr. Syst., 2009

An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.

Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.

Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Dynamic Compaction in SAT-Based ATPG.

Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.

Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Automatic Test Pattern Generation for Interconnect Open Defects.

Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.

Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng

Proceedings of the 2008 IEEE International Test Conference, 2008

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.

Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker

Proceedings of the 13th European Test Symposium, 2008

Diagnosis of Realistic Defects Based on the X-Fault Model.

Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Resistive Bridging Fault Simulation of Industrial Circuits.

Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Simulating Open-Via Defects.

Stefan Spinner, Jie Jiang, Ilia Polian, Piet Engelke, Bernd Becker

Proceedings of the 16th Asian Test Symposium, 2007

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges.

Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker

Proceedings of the 16th Asian Test Symposium, 2007

2006

X-masking during logic BIST and its impact on defect coverage.

Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke

IEEE Trans. Very Large Scale Integr. Syst., 2006

Simulating Resistive-Bridging and Stuck-At Faults.

Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Automatic Test Pattern Generation for Resistive Bridging Faults.

Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker

J. Electron. Test., 2006

A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency.

Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker

Proceedings of the 15th Asian Test Symposium, 2006

Delta-IDDQ Testing of Resistive Short Defects.

Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker

Proceedings of the 15th Asian Test Symposium, 2006

2005

Modeling Feedback Bridging Faults with Non-Zero Resistance.

Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker

J. Electron. Test., 2005

Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.

Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A unified fault model and test generation procedure for interconnect opens and bridges.

Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker

Proceedings of the 10th European Test Symposium, 2005

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.

Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.

Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

X-Masking During Logic BIST and Its Impact on Defect Coverage.

Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002

Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.

Ilia Polian, Piet Engelke, Bernd Becker

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2000

A parameterizable fault simulator for bridging faults.

Piet Engelke, Bernd Becker, Martin Keim

Proceedings of the 5th European Test Workshop, 2000