Pierre Vanhauwaert
According to our database1,
Pierre Vanhauwaert
authored at least 14 papers
between 2005 and 2018.
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Bibliography
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
2016
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
IEEE Trans. Multi Scale Comput. Syst., 2016
2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking.
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
2006
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005