Pierre Canet

According to our database, Pierre Canet authored at least 12 papers between 2000 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

True random number generation exploiting SET voltage variability in resistive RAM memory arrays.

Jérémy Postel-Pellerin, Hussein Bazzi, Hassen Aziza, Pierre Canet, Mathieu Moreau, Vincenzo Della Marca, Adnan Harb

Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

An Augmented OxRAM Synapse for Spiking Neural Network (SNN) Circuits.

Hassen Aziza, Hussein Bazzi, Jérémy Postel-Pellerin, Pierre Canet, Mathieu Moreau, Adnan Harb

Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

2016

Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories.

Pierre Canet, Jérémy Postel-Pellerin, Hassen Aziza

Microelectron. Reliab., 2016

2014

Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories.

Vincenzo Della Marca, Jérémy Postel-Pellerin, Guillaume Just, Pierre Canet, Jean-Luc Ogier

Microelectron. Reliab., 2014

2013

Access resistor modelling for EEPROM's retention test vehicle.

Pierre Canet, Jérémy Postel-Pellerin, Jean-Luc Ogier

Microelectron. Reliab., 2013

2009

Modeling charge variation during data retention of MLC Flash memories.

Jérémy Postel-Pellerin, Frédéric Lalande, Pierre Canet, Rachid Bouchakour, F. Jeuland, L. Morancho

Microelectron. Reliab., 2009

Extraction of 3D parasitic capacitances in 90 nm and 22 nm NAND flash memories.

Jérémy Postel-Pellerin, Frédéric Lalande, Pierre Canet, Rachid Bouchakour, F. Jeuland, B. Bertello, B. Villard

Microelectron. Reliab., 2009

2008

Flash Memory Cell Compact Modeling Using PSP Model.

Anthony Maure, Pierre Canet, Frédéric Lalande, Bertrand Delsuc, Jean Devin

Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008

2002

Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact.

Romain Laffont, J. Razafindramora, Pierre Canet, Rachid Bouchakour, Jean-Michel Mirabel

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

2001

EEPROM programming study-time and degradation aspects.

Pierre Canet, Rachid Bouchakour, Nadia Harabech, Philippe Boivin, Jean-Michel Mirabel

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect.

Rachid Bouchakour, Nadia Harabech, Pierre Canet, Philippe Boivin, Jean Michel Mirable

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Extraction of Fowler-Nordheim parameters of thin SiO₂ oxide film including polysilicon gate depletion: validation with an EEPROM memory cell.

Nadia Harabech, Rachid Bouchakour, Pierre Canet, Philippe Pannier, Jean-Pierre Sorbier

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000