Pierre Bisiaux

According to our database, Pierre Bisiaux authored at least 8 papers between 2016 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model.

Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina

IEEE Trans. Circuits Syst. II Express Briefs, 2021

All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance.

Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

FPGA Validation of Event-Driven ADPLL.

Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina

Proceedings of the European Conference on Circuit Theory and Design, 2020

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process.

Pierre Bisiaux, Elena Blokhina, Eugene Koskin, Teerachot Siriburanon, Dimitri Galayko

Proceedings of the European Conference on Circuit Theory and Design, 2020

2019

All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping.

Eugene Koskin, Pierre Bisiaux, Dimitri Galayko, Elena Blokhina

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018

Experimental Demonstration of a 65 nm Integrated CMOS Waveform Generator for 5G sub-6GHz Standard.

Pierre Bisiaux, Francois Rivet, Yoan Veyrac, Yann Deval

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor.

Pierre Bisiaux, Caroline Lelandais-Perrault, Anthony Kolar, Philippe Bénabès, Filipe Vinci dos Santos

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

2016

A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor.

Pierre Bisiaux, Caroline Lelandais-Perrault, Anthony Kolar, Philippe Bénabès, Filipe Vinci dos Santos

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016