Pierpaolo Palestri
Orcid: 0000-0002-1672-1166
According to our database1,
Pierpaolo Palestri
authored at least 44 papers
between 2005 and 2024.
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Bibliography
2024
From Finite Element Simulations to Equivalent Circuit Models of Extracellular Neuronal Recording Systems Based on Planar and Mushroom Electrodes.
IEEE Trans. Biomed. Eng., April, 2024
2023
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
Mitigation of Electrical/Ionic Interference in Iontronic Neurostimulation/Neurosensing Platforms: A Simulation Study.
Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023
Identification of Axon Bendings in Neurons by Multiphysics FEM Simulations of High-Density MEA Extracellular Recordings.
Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023
2022
Synchrotron Radiation Study of Gain, Noise, and Collection Efficiency of GaAs SAM-APDs with Staircase Structure.
Sensors, 2022
Multiphysics Finite-Element Modeling of the Neuron/Electrode Electrodiffusive Interaction.
Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022
2021
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Sensitivity, Noise and Resolution in a BEOL-Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications.
Sensors, 2021
A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS.
CoRR, 2021
2020
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020
2019
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces.
Proceedings of the 42nd International Convention on Information and Communication Technology, 2019
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
Design of a transmitter for high-speed serial interfaces in automotive micro-controller.
Proceedings of the 39th International Convention on Information and Communication Technology, 2016
Performance study of strained III-V materials for ultra-thin body transistor applications.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique.
Int. J. Circuit Theory Appl., 2015
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall.
Proceedings of the 1st IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2015
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015
Proceedings of the 45th European Solid State Device Research Conference, 2015
2014
Proceedings of the 37th International Convention on Information and Communication Technology, 2014
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Microscopic scale characterization and modeling of transistor degradation under HC stress.
Microelectron. Reliab., 2012
A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
2010
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators.
Int. J. Circuit Theory Appl., 2010
2009
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2005
PhD thesis, 2005
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.
IEEE J. Solid State Circuits, 2005