Pierluigi Civera

According to our database1, Pierluigi Civera authored at least 23 papers between 1982 and 2014.

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Bibliography

2014
Microvesicle fractionation using deterministic lateral displacement effect.
Proceedings of the 9th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2014

2013
A 0.13~µm CMOS Operational Schmitt Trigger R-to-F Converter for Nanogap-Based Nanosensors Read-Out.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A low-power Read-Out Circuit and low-cost assembly of nanosensors onto a 0.13 μm CMOS Micro-for-Nano chip.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

Integrated microcapillary system for microfluidic parasite analysis.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012
A Very Low-Complexity 0.3-4.4 GHz 0.004 mm<sup>2</sup> All-Digital Ultra-Wide-Band Pulsed Transmitter for Energy Detection Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2009
Wireless Sensor Networks for Intelligent Transportation Systems.
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

2008
MEMS-based blood cell counting system.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2003
New techniques for efficiently assessing reliability of SOCs.
Microelectron. J., 2003

2002
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits.
J. Electron. Test., 2002

A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Exploiting FPGA for Accelerating Fault Injection Experiments.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits.
Proceedings of the Field-Programmable Logic and Applications, 2001

Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits .
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

FPGA-Based Fault Injection for Microprocessor Systems.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
RTL Estimation of Steering Logic Power.
Proceedings of the Integrated Circuit Design, 2000

1999
Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998
Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

An Integrated HW and SW Fault Injection Environment for Real-Time Systems.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1992
Deflection network: Principles, implementation, services.
Eur. Trans. Telecommun., 1992

1989
Implementation studies for a VLSI Prolog coprocessor.
IEEE Micro, 1989

1987
Design considerations on a VLSI Prolog interpreter.
Microprocess. Microprogramming, 1987

An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results.
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

1982
The μ Project: An Experience with a Multimicroprocessor System.
IEEE Micro, 1982


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