Pierangelo Terreni

Affiliations:
  • University of Pisa, Italy


According to our database1, Pierangelo Terreni authored at least 34 papers between 1990 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2014
A Real-Time FPGA-based Solution for Binary Image Thinning.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

2012
Hardware building blocks of a hierarchical battery management system for a fuel cell HEV.
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012

2011
Sensor Modeling, Low-Complexity Fusion Algorithms, and Mixed-Signal IC Prototyping for Gas Measures in Low-Emission Vehicles.
IEEE Trans. Instrum. Meas., 2011

2010
Mixed-Signal Architectures for High-Efficiency and Low-Distortion Digital Audio Processing and Power Amplification.
EURASIP J. Embed. Syst., 2010

2009
Smart transducer interface in embedded systems for networked sensors based on the emerging IEEE 1451 Standard: H2 Detection Case Study.
Proceedings of the Seventh Workshop on Intelligent solutions in Embedded Systems, 2009

Sensor modeling and data fusion for a safety warning system in hydrogen-based vehicles.
Proceedings of the 2009 IEEE International Workshop on Robotic and Sensors Environments, 2009

Sensor modeling and fusion algorithms for NOx measures towards zero emissions vehicles.
Proceedings of the 2009 IEEE International Workshop on Robotic and Sensors Environments, 2009

2008
Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems.
IEICE Trans. Electron., 2008

2007
Architectural-Level Power Optimization of Microcontroller Cores in Embedded Systems.
IEEE Trans. Ind. Electron., 2007

Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Oversampled and Noise-Shaped Pulse-Width Modulator for High-Fidelity Digital Audio Amplifier.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Mixed-signal design of a digital input power amplifier for automotive audio applications.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Self-Adaptive Algorithmic/Architectural Design for Real-Time, Low-Power Video Systems.
IEICE Trans. Inf. Syst., 2005

Enriching an analog platform for analog-to-digital converter design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction.
EURASIP J. Adv. Signal Process., 2004

Context-Aware Algorithmic/Architectural Solutions for Real-time Embedded Video Systems.
Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems, 2004

Adaptive algorithm for fast motion estimation in H.264/MPEG-4 AVC.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

2003
A QoS Internet Protocol Scheduler on the IXP1200 Network Platform.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

2002
FAST: FFT ASIC automated synthesis.
Integr., 2002

VLSI design of a routing switch for the SpaceWire serial link standard.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

1999
An efficient VLSI architecture for real-time additive synthesis of musical signals.
IEEE Trans. Very Large Scale Integr. Syst., 1999

1998
Multihit multichannel time-to-digital converter with ±1% differential nonlinearity and near optimal time resolution.
IEEE J. Solid State Circuits, 1998

1997
A pyramid vector quantizer chip for HDTV applications.
Eur. Trans. Telecommun., 1997

Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

A single-chip 1, 200 sinusoid real-time generator for additive synthesis of musical signals.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1993
Linear networks and systems depending polynomially on parameters: Stability for large values subject to tolerance errors.
Int. J. Circuit Theory Appl., 1993

Linear networks and systems polynomially depending on parameters: Behaviour of the solutions for large and small values.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Conditions for the existence and uniqueness of DC solutions of networks containing nonlinear opamps with ideal model.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
Single-chip adaptive FIR filter for acoustic echo canceller board.
Signal Process., 1992

ASIC-based acoustic echo-canceller board for VME bus.
Eur. Trans. Telecommun., 1992

1990
An example of a new VLSI design style based on systolic macrocells: A high-speed single-chip transversal filter for signal processing applications.
Eur. Trans. Telecommun., 1990


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