Phiroze N. Parakh

According to our database1, Phiroze N. Parakh authored at least 7 papers between 1998 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2008
A robust approach to lithography friendly design implementation.
Proceedings of the 2008 International Symposium on Physical Design, 2008

2004
Benchmarking for large-scale placement and beyond.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2000
CGaAs PowerPC FXU.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Crosstalk constrained global route embedding.
Proceedings of the 1999 International Symposium on Physical Design, 1999

1998
Overview of complementary GaAs technology for high-speed VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Congestion Driven Quadratic Placement.
Proceedings of the 35th Conference on Design Automation, 1998


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