Philippos Papaphilippou

According to our database, Philippos Papaphilippou authored at least 23 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers.

Philippos Papaphilippou, Thiem Van Chu

IEEE Trans. Computers, May, 2024

Revisiting 3D Cartesian Scatterplots with a Novel Plotting Framework and a Survey.

Philippos Papaphilippou

CoRR, 2024

Efficient Adaptable Streaming Aggregation Engine.

Philippos Papaphilippou, Wayne Luk

CoRR, 2024

2023

Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer.

Philippos Papaphilippou, Kentaro Sano, Boma Anantasatya Adhi, Wayne Luk

IEEE Trans. Parallel Distributed Syst., May, 2023

Efficient deadlock avoidance in 2D mesh NoCs that use OQ or VOQ routers.

Philippos Papaphilippou

CoRR, 2023

Efficiently Removing Sparsity for High-Throughput Stream Processing.

Philippos Papaphilippou, Zhiqiang Que, Wayne Luk

Proceedings of the International Conference on Field Programmable Technology, 2023

2022

Hipernetch: High-Performance FPGA Network Switch.

Philippos Papaphilippou, Jiuxi Meng, Nadeen Gebara, Wayne Luk

ACM Trans. Reconfigurable Technol. Syst., 2022

FLiMS: A Fast Lightweight 2-Way Merger for Sorting.

Philippos Papaphilippou, Wayne Luk, Chris Brooks

IEEE Trans. Computers, 2022

FPGA-extended Modified Harvard Architecture.

Philippos Papaphilippou

CoRR, 2022

FPGA-Extended General Purpose Computer Architecture.

Philippos Papaphilippou, Myrtle Shah

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022

2021

FLiMS: a Fast Lightweight 2-way Merge Sorter.

Philippos Papaphilippou, Wayne Luk, Chris Brooks

CoRR, 2021

Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions.

Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk

CoRR, 2021

Efficient Queue-Balancing Switch for FPGAs.

Philippos Papaphilippou, Kentaro Sano, Boma A. Adhi, Wayne Luk

Proceedings of the International Conference on Field-Programmable Technology, 2021

Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions.

Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Demonstrating custom SIMD instruction development for a RISC-V softcore.

Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020

An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics.

Philippos Papaphilippou, Chris Brooks, Wayne Luk

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

High-Performance FPGA Network Switch Architecture.

Philippos Papaphilippou, Jiuxi Meng, Wayne Luk

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019

Accelerating Hybrid Monte Carlo simulations of the Hubbard model on the hexagonal lattice.

Stefan Krieg, Thomas Luu, Johann Ostmeyer, Philippos Papaphilippou, Carsten Urbach

Comput. Phys. Commun., 2019

Pangloss: a novel Markov chain prefetcher.

Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk

CoRR, 2019

Accelerating the Merge Phase of Sort-Merge Join.

Philippos Papaphilippou, Holger Pirk, Wayne Luk

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018

Performance tuning for deep learning on a many-core processor (master thesis).

Philippos Papaphilippou

CoRR, 2018

FLiMS: Fast Lightweight Merge Sorter.

Philippos Papaphilippou, Chris Brooks, Wayne Luk

Proceedings of the International Conference on Field-Programmable Technology, 2018

Accelerating Database Systems Using FPGAs: A Survey.

Philippos Papaphilippou, Wayne Luk

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018