Philippe Coppejans

According to our database, Philippe Coppejans authored at least 6 papers between 2002 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A Highly-Integrated 1536-Channel Quad-Shank Monolithic Neural Probe in 55nm CMOS for Full-Band Raw-Signal Recording.

Xiaolin Yang, Joan Aymerich, Philippe Coppejans, Wen-Yang Hsu, Chutham Sawigun, Jose Cisneros-Fernández, Andrea Lodi, Maribel Caceres Rivera, Bernardo Tacca, Matt McDonald, Hasan Mahmud-UI, Barundeb Dutta, Jan Putzeys, Carolina Mora Lopez

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range.

Wen-Yang Hsu, Joan Aymerich, Xiaolin Yang, Chutham Sawigun, Philippe Coppejans, Carolina Mora Lopez

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2018

Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification.

Lin-Kun Wu, David San Segundo Bello, Philippe Coppejans, Jan Craninckx, Andreas Süss, Maarten Rosmeulen, Piet Wambacq, Jonathan Borremans

Sensors, 2018

2003

Dynamic biasing: a low power linearisation technique.

Philippe Coppejans, Michiel Steyaert

Proceedings of the ESSCIRC 2003, 2003

2002

Optimization of a fully integrated low power CMOS GPS receiver.

Peter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Paul Leroux, Michiel Steyaert

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A quadrature direct digital downconverter.

Peter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Michiel Steyaert

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002