Philip Pan
According to our database1,
Philip Pan
authored at least 3 papers
between 2004 and 2009.
Collaborative distances:
Collaborative distances:
Timeline
2004
2005
2006
2007
2008
2009
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
2005
A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface.
IEEE J. Solid State Circuits, 2005
2004
A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004