Instruction generation and regularity extraction for reconfigurable processors. - Philip Brisk; Adam Kaplan; Ryan Kastner; Majid Sarrafzadeh (CASES, 2002)

Data communication estimation and reduction for reconfigurable systems. - Adam Kaplan; Philip Brisk; Ryan Kastner (DAC, 2003)

Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. - Philip Brisk; Adam Kaplan; Majid Sarrafzadeh (DAC, 2004)

Instruction Selection for Compilers that Target Architectures with Echo Instructions. - Philip Brisk; Ani Nahapetian; Majid Sarrafzadeh (SCOPES, 2004)

A dictionary construction technique for code compression systems with echo instructions. - Philip Brisk; Jamie Macbeth 001; Ani Nahapetian; Majid Sarrafzadeh (LCTES, 2005)

Adaptive and fault tolerant medical vest for life-critical medical monitoring. - Roozbeh Jafari; Foad Dabiri; Philip Brisk; Majid Sarrafzadeh (SAC, 2005)

Layout driven data communication optimization for high level synthesis. - Ryan Kastner; Wenrui Gong; Xin Hao; Forrest Brewer; Adam Kaplan; Philip Brisk; Majid Sarrafzadeh (DATE, 2006)

Optimal register sharing for high-level synthesis of SSA form programs. - Philip Brisk; Foad Dabiri; Roozbeh Jafari; Majid Sarrafzadeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Delay aware, reconfigurable security for embedded systems. - Tammara Massey; Philip Brisk; Foad Dabiri; Majid Sarrafzadeh (BODYNETS, 2007)

An optimistic and conservative register assignment heuristic for chordal graphs. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne (CASES, 2007)

Rethinking custom ISE identification: a new processor-agnostic method. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (CASES, 2007)

Enhancing FPGA Performance for Arithmetic Circuits. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne; Hadi Parandeh-Afshar (DAC, 2007)

Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (DAC, 2007)

Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne (ICCAD, 2007)

Interference graphs for procedures in static single information form are interval graphs. - Philip Brisk; Majid Sarrafzadeh (SCOPES, 2007)

Efficient synthesis of compressor trees on FPGAs. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (ASP-DAC, 2008)

Fast, quasi-optimal, and pipelined instruction-set extensions. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (ASP-DAC, 2008)

Design space exploration for field programmable compressor trees. - Seyed-Hosein Attarzadeh-Niaki; Alessandro Cevrero; Philip Brisk; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (CASES, 2008)

Speculative DMA for architecturally visible storage in instruction set extensions. - Theo Kluter; Philip Brisk; Paolo Ienne; Edoardo Charbon (CODES+ISSS, 2008)

Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (DATE, 2008)

Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (DATE, 2008)

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Philip Brisk; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (FPGA, 2008)

A novel FPGA logic block for improved arithmetic performance. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (FPGA, 2008)

Scheduling of dataflow models within the Reconfigurable Video Coding framework. - Jani Boutellier; Veeranjaneyulu Sadhanala; Christophe Lucarz; Philip Brisk; Marco Mattavelli (SiPS, 2008)

Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Challenges in Automatic Optimization of Arithmetic Circuits. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (IEEE Symposium on Computer Arithmetic, 2009)

Hybrid LZA: a near optimal implementation of the leading zero anticipator. - Amit Verma 002; Ajay Kumar Verma; Philip Brisk; Paolo Ienne (ASP-DAC, 2009)

A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. - Francesco Regazzoni 001; Alessandro Cevrero; François-Xavier Standaert; Stéphane Badel; Theo Kluter; Philip Brisk; Yusuf Leblebici; Paolo Ienne (CHES, 2009)

Thermal-aware data flow analysis. - José Luis Ayala; David Atienza; Philip Brisk (DAC, 2009)

Way Stealing: cache-assisted automatic instruction set extensions. - Theo Kluter; Philip Brisk; Paolo Ienne; Edoardo Charbon (DAC, 2009)

FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. - Arun Paidimarri; Alessandro Cevrero; Philip Brisk; Paolo Ienne (FCCM, 2009)

3D configuration caching for 2D FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Philip Brisk; Yusuf Leblebici; Paolo Ienne; Maurizio Skerlj (FPGA, 2009)

Using 3D integration technology to realize multi-context FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Maurizio Skerlj; Philip Brisk; Yusuf Leblebici; Paolo Ienne (FPL, 2009)

Exploiting fast carry-chains of FPGAs for designing compressor trees. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (FPL, 2009)

A flexible DSP block to enhance FPGA arithmetic performance. - Hadi Parandeh-Afshar; Alessandro Cevrero; Panagiotis Athanasopoulos; Philip Brisk; Yusuf Leblebici; Paolo Ienne (FPT, 2009)

MPSoC Design Using Application-Specific Architecturally Visible Communication. - Theo Kluter; Philip Brisk; Edoardo Charbon; Paolo Ienne (HiPEAC, 2009)

Memory organization and data layout for instruction set extensions with architecturally visible storage. - Panagiotis Athanasopoulos; Philip Brisk; Yusuf Leblebici; Paolo Ienne (ICCAD, 2009)

Iterative layering: Optimizing arithmetic circuits by structuring the information flow. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (ICCAD, 2009)

Arithmetic optimization for custom instruction set synthesis. - Ajay Kumar Verma; Yi Zhu; Philip Brisk; Paolo Ienne (SASP, 2009)

Introducing control-flow inclusion to support pipelining in custom instruction set extensions. - Marcela Zuluaga; Theo Kluter; Philip Brisk; Nigel P. Topham; Paolo Ienne (SASP, 2009)

Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. - Jani Boutellier; Alessandro Cevrero; Philip Brisk; Paolo Ienne (SiPS, 2009)

Optimistic chordal coloring: a coalescing heuristic for SSA form programs. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne (Des. Autom. Embed. Syst., 2009)

An approximation algorithm for scheduling on heterogeneous reconfigurable resources. - Ani Nahapetian; Philip Brisk; Soheil Ghiasi; Majid Sarrafzadeh (ACM Trans. Embed. Comput. Syst., 2009)

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Seyed-Hosein Attarzadeh-Niaki; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Philip Brisk; Yusuf Leblebici; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2009)

An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2009)

A high-level synthesis flow for custom instruction set extensions for application-specific processors. - Nagaraju Pothineni; Philip Brisk; Paolo Ienne; Anshul Kumar; Kolin Paul (ASP-DAC, 2010)

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. - Amit Verma 002; Ajay Kumar Verma; Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (FPL, 2010)

Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. - Theo Kluter; Samuel Burri; Philip Brisk; Edoardo Charbon; Paolo Ienne (HiPEAC, 2010)

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. - Ajay Kumar Verma; Philip Brisk; Paolo Ienne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Improving FPGA Performance for Carry-Save Arithmetic. - Hadi Parandeh-Afshar; Ajay Kumar Verma; Philip Brisk; Paolo Ienne (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Architecture and design automation for application-specific processors. - Philip Brisk (ASICON, 2011)

Graph-coloring and treescan register allocation using repairing. - Quentin Colombet; Benoit Boissinot; Philip Brisk; Sebastian Hack; Fabrice Rastello (CASES, 2011)

A first step towards automatic application of power analysis countermeasures. - Ali Galip Bayrak; Francesco Regazzoni 001; Philip Brisk; François-Xavier Standaert; Paolo Ienne (DAC, 2011)

Reducing the pressure on routing resources of FPGAs with generic logic chains. - Hadi Parandeh-Afshar; Grace Zgheib; Philip Brisk; Paolo Ienne (FPGA, 2011)

Compressor tree synthesis on commercial high-performance FPGAs. - Hadi Parandeh-Afshar; Arkosnato Neogy; Philip Brisk; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2011)

Fast online synthesis of generally programmable digital microfluidic biochips. - Daniel T. Grissom; Philip Brisk (CODES+ISSS, 2012)

Path scheduling on digital microfluidic biochips. - Daniel T. Grissom; Philip Brisk (DAC, 2012)

Selective flexibility: Breaking the rigidity of datapath merging. - Mirjana Stojilovic; David Novo; Lazar Saranovac; Philip Brisk; Paolo Ienne (DATE, 2012)

Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. - Yehdhih Ould Mohammed Moctar; Nithin George; Hadi Parandeh-Afshar; Paolo Ienne; Guy G. F. Lemieux; Philip Brisk (FPGA, 2012)

Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. - Yehdhih Ould Mohammed Moctar; Guy G. F. Lemieux; Philip Brisk (FPL, 2012)

A high-performance online assay interpreter for digital microfluidic biochips. - Daniel T. Grissom; Philip Brisk (ACM Great Lakes Symposium on VLSI, 2012)

Counting stream registers: An efficient and effective snoop filter architecture. - Aanjhan Ranganathan; Ali Galip Bayrak; Theo Kluter; Philip Brisk; Edoardo Charbon; Paolo Ienne (ICSAMOS, 2012)

A digital microfluidic biochip synthesis framework. - Daniel T. Grissom; Kenneth O'Neal; Benjamin Preciado; Hiral Patel; Robert Doherty; Nick Liao; Philip Brisk (VLSI-SoC, 2012)

Force-Directed List Scheduling for Digital Microfluidic Biochips. - Kenneth O'Neal; Daniel T. Grissom; Philip Brisk (VLSI-SoC, 2012)

SSI Properties Revisited. - Benoit Boissinot; Philip Brisk; Alain Darte; Fabrice Rastello (ACM Trans. Embed. Comput. Syst., 2012)

Design and verification tools for continuous fluid flow-based microfluidic devices. - Jeffrey McDaniel; Auralila Baez; Brian Crites; Aditya Tammewar; Philip Brisk (ASP-DAC, 2013)

Automatic synthesis of microfluidic large scale integration chips from a domain-specific language. - Jeffrey McDaniel; Christopher Curtis; Philip Brisk (BioCAS, 2013)

Instruction set extensions for Dynamic Time Warping. - Joseph Tarango; Eamonn J. Keogh; Philip Brisk (CODES+ISSS, 2013)

A field-programmable pin-constrained digital microfluidic biochip. - Daniel T. Grissom; Philip Brisk (DAC, 2013)

An EDA-friendly protection scheme against side-channel attacks. - Ali Galip Bayrak; Nikola Velickovic; Francesco Regazzoni 001; David Novo; Philip Brisk; Paolo Ienne (DATE, 2013)

Shared memory heterogeneous computation on PCIe-supported platforms. - Sambit Kumar Shukla; Yang Yang 111; Laxmi N. Bhuyan; Philip Brisk (FPL, 2013)

A just-in-time customizable processor. - Liang Chen; Joseph Tarango; Tulika Mitra; Philip Brisk (ICCAD, 2013)

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. - Mirjana Stojilovic; David Novo; Lazar Saranovac; Philip Brisk; Paolo Ienne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Introduction to the special issue on application-specific processors. - Philip Brisk; Tulika Mitra (ACM Trans. Embed. Comput. Syst., 2013)

Accelerating the dynamic time warping distance measure using logarithmetic arithmetic. - Joseph Tarango; Eamonn J. Keogh; Philip Brisk (ACSSC, 2014)

Exploring speed and energy tradeoffs in droplet transport for digital microfluidic biochips. - Johnathan Fiske; Daniel T. Grissom; Philip Brisk (ASP-DAC, 2014)

Parallel FPGA Routing based on the Operator Formulation. - Yehdhih Ould Mohammed Moctar; Philip Brisk (DAC, 2014)

Performance and cost analysis of NoC-inspired virtual topologies for digital microfluidic biochips. - Daniel T. Grissom; Jeffrey McDaniel; Philip Brisk (ISIC, 2014)

Multi-terminal PCB escape routing for digital microfluidic biochips using negotiated congestion. - Jeffrey McDaniel; Daniel T. Grissom; Philip Brisk (VLSI-SoC, 2014)

Simulated annealing-based placement for microfluidic large scale integration (mLSI) chips. - Jeffrey McDaniel; Brendon Parker; Philip Brisk (VLSI-SoC, 2014)

Interpreting Assays with Control Flow on Digital Microfluidic Biochips. - Daniel T. Grissom; Christopher Curtis; Philip Brisk (ACM J. Emerg. Technol. Comput. Syst., 2014)

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. - Theo Kluter; Samuel Burri; Philip Brisk; Edoardo Charbon; Paolo Ienne (ACM Trans. Archit. Code Optim., 2014)

Fast Online Synthesis of Digital Microfluidic Biochips. - Daniel T. Grissom; Philip Brisk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A Low-Cost Field-Programmable Pin-Constrained Digital Microfluidic Biochip. - Daniel T. Grissom; Jeffrey McDaniel; Philip Brisk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. - Theo Kluter; Philip Brisk; Edoardo Charbon; Paolo Ienne (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Rapid online fault recovery for cyber-physical digital microfluidic biochips. - Christopher Jaress; Philip Brisk; Daniel T. Grissom (VTS, 2015)

Flow-Layer Physical Design for Microchips Based on Monolithic Membrane Valves. - Jeffrey McDaniel; Brian Crites; Philip Brisk; William H. Grover (IEEE Des. Test, 2015)

An open-source compiler and PCB synthesis tool for digital microfluidic biochips. - Daniel T. Grissom; Christopher Curtis; Skyler Windh; Calvin Phung; Navin Kumar; Zachary Zimmerman; Kenneth O'Neal; Jeffrey McDaniel; Nick Liao; Philip Brisk (Integr., 2015)

Automatic Application of Power Analysis Countermeasures. - Ali Galip Bayrak; Francesco Regazzoni 001; David Novo; Philip Brisk; François-Xavier Standaert; Paolo Ienne (IEEE Trans. Computers, 2015)

Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars. - Yehdhih Ould Mohammed Moctar; Guy G. F. Lemieux; Philip Brisk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation. - Bailey Miller; Frank Vahid; Tony Givargis; Philip Brisk (ACM Trans. Reconfigurable Technol. Syst., 2015)

Preface. - Paolo Ienne; Walid A. Najjar; Jason Helge Anderson; Philip Brisk; Walter Stechele (FPL, 2016)

Matrix Profile II: Exploiting a Novel Algorithm and GPUs to Break the One Hundred Million Barrier for Time Series Motifs and Joins. - Yan Zhu 014; Zachary Zimmerman; Nader Shakibay Senobari; Chin-Chia Michael Yeh; Gareth J. Funning; Abdullah Mueen; Philip Brisk; Eamonn J. Keogh (ICDM, 2016)

From C to elastic circuits. - Lana Josipovic; Philip Brisk; Paolo Ienne (ACSSC, 2017)

Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. - Andrew Becker; Wei Hu 008; Yu Tai; Philip Brisk; Ryan Kastner; Paolo Ienne (DAC, 2017)

HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs. - Kenneth O'Neal; Philip Brisk; Emily Shriver; Michael Kishinevsky (DAC, 2017)

The case for semi-automated design of microfluidic very large scale integration (mVLSI) chips. - Jeffrey McDaniel; William H. Grover; Philip Brisk (DATE, 2017)

CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design. - Sina Boroumand; Hadi Parandeh-Afshar; Philip Brisk; Siamak Mohammadi (DFT, 2017)

Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving. - Brian Crites; Karen Kong; Philip Brisk (ACM Great Lakes Symposium on VLSI, 2017)

Design Automation for Paper Microfluidics with Passive Flow Substrates. - Joshua Potter; William H. Grover; Philip Brisk (ACM Great Lakes Symposium on VLSI, 2017)

PCB Escape Routing and Layer Minimization for Digital Microfluidic Biochips. - Jeffrey McDaniel; Zachary Zimmerman; Daniel T. Grissom; Philip Brisk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Performance Improvements and Congestion Reduction for Routing-Based Synthesis for Digital Microfluidic Biochips. - Skyler Windh; Calvin Phung; Daniel T. Grissom; Paul Pop; Philip Brisk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Diagonal Component Expansion for Flow-Layer Placement of Flow-Based Microfluidic Biochips. - Brian Crites; Karen Kong; Philip Brisk (ACM Trans. Embed. Comput. Syst., 2017)

An Out-of-Order Load-Store Queue for Spatial Computing. - Lana Josipovic; Philip Brisk; Paolo Ienne (ACM Trans. Embed. Comput. Syst., 2017)

GPU Performance Estimation using Software Rasterization and Machine Learning. - Kenneth O'Neal; Philip Brisk; Ahmed Abousamra; Zack Waters; Emily Shriver (ACM Trans. Embed. Comput. Syst., 2017)

Exploration of approximate multipliers design space using carry propagation free compressors. - Sina Boroumand; Hadi Parandeh-Afshar; Philip Brisk; Siamak Mohammadi (ASP-DAC, 2018)

A compiler for cyber-physical digital microfluidic biochips. - Christopher Curtis; Daniel T. Grissom; Philip Brisk (CGO, 2018)

Approximate quaternary addition with the fast carry chains of FPGAs. - Sina Boroumand; Hadi Parandeh-Afshar; Philip Brisk (DATE, 2018)

Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model. - Yehdhih Ould Mohammed Moctar; Mirjana Stojilovic; Philip Brisk (FPL, 2018)

HLSPredict: cross platform performance prediction for FPGA high-level synthesis. - Kenneth O'Neal; Mitch Liu; Hans Tang; Amin Kalantar; Kennen DeRenard; Philip Brisk (ICCAD, 2018)

ParchMint: A Microfluidics Benchmark Suite. - Brian Crites; Radhakrishna Sanka; Joshua Lippai; Jeffrey McDaniel; Philip Brisk; Douglas Densmore (IISWC, 2018)

Predictive Modeling for CPU, GPU, and FPGA Performance and Power Consumption: A Survey. - Kenneth O'Neal; Philip Brisk (ISVLSI, 2018)

Accelerating Simulation of Particle Trajectories in Microfluidic Devices by Constructing a Cloud Database. - Junchao Wang; Lingxuan Fu; Liyang Yu; Xiwei Huang; Philip Brisk; William H. Grover (ISVLSI, 2018)

Resource-Constrained Scheduling for Digital Microfluidic Biochips. - Kenneth O'Neal; Daniel T. Grissom; Philip Brisk (ACM J. Emerg. Technol. Comput. Syst., 2018)

Exploiting a novel algorithm and GPUs to break the ten quadrillion pairwise comparisons barrier for time series motifs and joins. - Yan Zhu 014; Zachary Zimmerman; Nader Shakibay Senobari; Chin-Chia Michael Yeh; Gareth J. Funning; Abdullah Mueen; Philip Brisk; Eamonn J. Keogh (Knowl. Inf. Syst., 2018)

Stationary-Mixing Field-Programmable Pin-Constrained Digital Microfluidic Biochip. - Alireza Abdoli; Philip Brisk (Microelectron. J., 2018)

Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip. - Wajid Hassan Minhass; Jeffrey McDaniel; Michael Lander Raagaard; Philip Brisk; Paul Pop; Jan Madsen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Matrix Profile XIV: Scaling Time Series Motif Discovery with GPUs to Break a Quintillion Pairwise Comparisons a Day and Beyond. - Zachary Zimmerman; Kaveh Kamgar; Nader Shakibay Senobari; Brian Crites; Gareth J. Funning; Philip Brisk; Eamonn J. Keogh (SoCC, 2019)

Specification, Integration, and Benchmarking of Continuous Flow Microfluidic Devices: Invited Paper. - Radhakrishna Sanka; Brian Crites; Jeffrey McDaniel; Philip Brisk; Douglas Densmore (ICCAD, 2019)

Matrix Profile XVIII: Time Series Mining in the Face of Fast Moving Streams using a Learned Approximate Matrix Profile. - Zachary Zimmerman; Nader Shakibay Senobari; Gareth J. Funning; Evangelos E. Papalexakis; Samet Oymak; Philip Brisk; Eamonn J. Keogh (ICDM, 2019)

Oligo-Snoop: A Non-Invasive Side Channel Attack Against DNA Synthesis Machines. - Sina Faezi; Sujit Rokka Chhetri; Arnav Vaibhav Malawade; John Charles Chaput; William H. Grover; Philip Brisk; Mohammad Abdullah Al Faruque (NDSS, 2019)

Approximate Adder Tree Synthesis for FPGAs. - Sina Boroumand; Philip Brisk (ReConFig, 2019)

TCAD EIC Message: February 2019. - Philip Brisk; Suman Chakraborty; Claudionor Coelho; Abdoulaye Gamatié; Swaroop Ghosh; Xun Jiao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Hardware-Assisted Cross-Generation Prediction of GPUs Under Design. - Kenneth O'Neal; Philip Brisk; Emily Shriver; Michael Kishinevsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A performance-optimizing compiler for cyber-physical digital microfluidic biochips. - Tyson Loveless; Jason Ott; Philip Brisk (CGO, 2020)

Acoustic Side Channel Attack Against DNA Synthesis Machines: Poster Abstract. - Sina Faezi; Sujit Rokka Chhetri; Arnav Vaibhav Malawade; John Charles Chaput; William H. Grover; Philip Brisk; Mohammad Abdullah Al Faruque (ICCPS, 2020)

Tuning floating-point precision using dynamic program information and temporal locality. - Hugo Brunie; Costin Iancu; Khaled Z. Ibrahim; Philip Brisk; Brandon Cook 001 (SC, 2020)

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. - Frédéric Gessler; Philip Brisk; Mirjana Stojilovic (VLSID, 2020)

ChemStor: Using Formal Methods To Guarantee Safe Storage and Disposal of Chemicals. - Jason Ott; Daniel Tan; Tyson Loveless; William H. Grover; Philip Brisk (J. Chem. Inf. Model., 2020)

Directed Placement for mVLSI Devices. - Brian Crites; Karen Kong; Philip Brisk (ACM J. Emerg. Technol. Comput. Syst., 2020)

Matrix Profile Index Approximation for Streaming Time Series. - Maryam Shahcheraghi; Trevor Cappon; Samet Oymak; Evangelos E. Papalexakis; Eamonn J. Keogh; Zachary Zimmerman; Philip Brisk (IEEE BigData, 2021)

FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity Prediction. - Amin Kalantar; Zachary Zimmerman; Philip Brisk (FCCM, 2021)

Time- and resource-constrained scheduling for digital microfluidic biochips. - Tyson Loveless; Jason Ott; Philip Brisk (ICCPS, 2021)

BioScript: programming safe chemistry on laboratories-on-a-chip. - Jason Ott; Tyson Loveless; Christopher Curtis; Mohsen Lesani; Philip Brisk (Commun. ACM, 2021)

Reducing Microfluidic Very Large-Scale Integration (mVLSI) Chip Area by Seam Carving. - Brian Crites; Cody Falzone; Tristan Lopez; Karen Kong; Philip Brisk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Dynamic Radial Placement and Routing in Paper Microfluidics. - Joshua Potter; William H. Grover; Philip Brisk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Properties and Flavours. - Philip Brisk; Fabrice Rastello (SSA-based Compiler Design, 2022)

Hardware Compilation Using SSA. - Pedro C. Diniz; Philip Brisk (SSA-based Compiler Design, 2022)

Compiling Functions onto Digital Microfluidics. - Tyson Loveless; Philip Brisk (CGO, 2023)

Feature Extraction Accelerator for Streaming Time Series. - Prithviraj Yuvaraj; Amin Akalantar; Eamonn J. Keogh; Philip Brisk (FCCM, 2023)

FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge. - Amin Kalantar; Zachary Zimmerman; Philip Brisk (ACM Trans. Reconfigurable Technol. Syst., 2023)

Error detection using pneumatic logic. - Shane Hoang; Mabel Shehada; Zinal Patel; Minh-Huy Tran; Konstantinos Karydis; Philip Brisk; William H. Grover (CoRR, 2024)