Phil Nigh

According to our database1, Phil Nigh authored at least 40 papers between 1988 and 2016.

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Bibliography

2016
Testing in the year 2024 - big changes are coming.
Proceedings of the 21th IEEE European Test Symposium, 2016

2014
Board manufacturing test correlation to IC manufacturing test.
Proceedings of the 2014 International Test Conference, 2014

2013
Adaptive testing - Cost reduction through test pattern sampling.
Proceedings of the 2013 IEEE International Test Conference, 2013

2012
Physically-Aware N-Detect Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Guest Editors' Introduction: Yield Learning Processes and Methods.
IEEE Des. Test Comput., 2012

How are failure modes, defect types and test methods changing for 32nm/28nm technologies and beyond?
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
Industry leaders panel - How will testing change in the next 10 years?
Proceedings of the 2011 IEEE International Test Conference, 2011

Using well/substrate bias manipulation to enhance voltage-test-based defect detection.
Proceedings of the 2011 IEEE International Test Conference, 2011

2009
Application of non-parametric statistics of the parametric response for defect diagnosis.
Proceedings of the 2009 IEEE International Test Conference, 2009

2008
How Many Test Patterns are Useless?
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon.
Proceedings of the 2008 IEEE International Test Conference, 2008

The Evolving Role of Test ... it is now a "Value Add" Operation.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

2006
Guest Editor's Introduction: Evolving Methods for Detecting and Handling Reliability Defects.
IEEE Des. Test Comput., 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2005
Defect-Oriented Test for Ultra-Low DPM.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Redefining ATE: "Data Collection Engines that Drive Yield Learning and Process Optimization".
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Achieving Quality Levels of 100dpm: It's possible - but roll up your sleeves and be prepared to do some work..
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
The Increasing Importance of On-line Testing to Ensure High-Reliability Products.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Debating the Future of Burn-In.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Scan-Based Testing: The Only Practical Solution for Testing ASIC/Consumer Products.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
MINVDD Testing for Weak CMOS ICs.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000
Test method evaluation experiments and data.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Best Methods for At-Speed Testing?
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

SIA Roadmap: test must not limit future technologies.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Diagnosis and characterization of timing-related defects by time-dependent light emission.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Binning for IC Quality: Experimental Studies on the SEMATECH Data.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Application and Analysis of IDDQ Diagnostic Software.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Volume Manufacturing - ICs and Boards: DFT to the Rescue?
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1994
ASIC Test Cost/Strategy Trade-offs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1990
Test Generation for Current Testing (CMOS ICs).
IEEE Des. Test Comput., 1990

1989
Layout-driven test generation.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
Current sensing for built-in testing of CMOS circuits.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Testing oriented analysis of CMOS ICs with opens.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Built-in current testing-feasibility study.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988


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