Petru Cascaval

Orcid: 0000-0001-5382-0940

According to our database1, Petru Cascaval authored at least 12 papers between 2001 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Search Algorithm for Optimal Synthesis of Decoder for RAMs with Error-Correcting Codes.
Proceedings of the 26th International Conference on System Theory, Control and Computing , 2022

2020
Optimization Methods for Redundancy Allocation in Large Systems.
Vietnam. J. Comput. Sci., 2020

2019
March test algorithm for unlinked static reduced three-cell coupling faults in random-access memories.
Microelectron. J., 2019

01IP and QUBO: Optimization Methods for Redundancy Allocation in Complex Systems.
Proceedings of the 23rd International Conference on System Theory, Control and Computing, 2019

Active Redundancy Allocation in Complex Systems by Using Different Optimization Methods.
Proceedings of the Computational Collective Intelligence - 11th International Conference, 2019

An Evaluation of Various Regression Models for the Prediction of Two-Terminal Network Reliability.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2019: Theoretical Neural Computation, 2019

2018
Approximate Method to Evaluate Reliability of Complex Networks.
Complex., 2018

2017
SDP algorithm for network reliability evaluation.
Proceedings of the IEEE International Conference on INnovations in Intelligent SysTems and Applications, 2017

2010
March SR3C: A Test for a reduced model of all static simple three-cell coupling faults in random-access memories.
Microelectron. J., 2010

2005
Fault Tolerant Memory System with Active Redundancy for Critical Applications.
Int. J. Comput., 2005

2004
Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories.
J. Electron. Test., 2004

2001
Efficient march test for 3-coupling faults in random access memories.
Microprocess. Microsystems, 2001


  Loading...