Petr Fiser

According to our database, Petr Fiser authored at least 58 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

On the Influence of the Laser Illumination on the Logic Cells Current Consumption.

Dmytro Petryk, Zoya Dyka, Milos Krstic, Jan Belohoubek, Petr Fiser, Frantisek Steiner, Tomás Blecha, Peter Langendörfer, Ievgen Kabin

CoRR, 2024

Adaptive Input Normalization for Quantized Neural Networks.

Jan Schmidt, Petr Fiser, Miroslav Skrbek

Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks.

Jan Schmidt, Petr Fiser, Miroslav Skrbek

Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

2023

Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring.

Subrata Das, Arighna Deb, Petr Fiser

Proceedings of the International Symposium on Devices, Circuits and Systems, 2023

On the Influence of the Laser Illumination on the Logic Cells Current Consumption : First measurement results.

Dmytro Petryk, Zoya Dyka, Milos Krstic, Jan Belohoubek, Petr Fiser, Frantisek Steiner, Tomás Blecha, Peter Langendörfer, Ievgen Kabin

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Reducing Output Response Aliasing Using Boolean Optimization Techniques.

Robert Hülle, Petr Fiser, Jan Schmidt

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022

A Design Space Exploration Framework for Memristor-Based Crossbar Architecture.

Mario Barbareschi, Alberto Bosio, Ian O'Connor, Petr Fiser, Marcello Traiola

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021

Minimization of Switching Activity of Graphene Based Circuits.

Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Emerging Technologies: Challenges and Opportunities for Logic Synthesis.

Alberto Bosio, Mayeul Cantan, Cédric Marchand, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020

Special issue on DSD 2018.

Martin Novotný, Petr Fiser

Microprocess. Microsystems, 2020

Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing.

Jaroslav Borecký, Robert Hülle, Petr Fiser

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Standard Cell Tuning Enables Data-Independent Static Power Consumption.

Jan Belohoubek, Petr Fiser, Jan Schmidt

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019

SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support.

Petr Fiser, Ivo Hálecek, Jan Schmidt, Václav Simek

J. Circuits Syst. Comput., 2019

CMOS Illumination Discloses Processed Data.

Jan Belohoubek, Petr Fiser, Jan Schmidt

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Using Voters May Lead to Secret Leakage.

Jan Belohoubek, Petr Fiser, Jan Schmidt

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018

Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR.

Ivo Hálecek, Petr Fiser, Jan Schmidt

Microelectron. Reliab., 2018

ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction.

Robert Hülle, Petr Fiser, Jan Schmidt

Microprocess. Microsystems, 2018

Optimum polymorphic circuits synthesis method.

Petr Fiser, Václav Simek

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Synthesis of Finite State Machines on Memristor Crossbars.

Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017

Error masking method based on the short-duration offline test.

Jan Belohoubek, Petr Fiser, Jan Schmidt

Microprocess. Microsystems, 2017

SAT-Based ATPG for Zero-Aliasing Compaction.

Robert Hülle, Petr Fiser, Jan Schmidt

Proceedings of the Euromicro Conference on Digital System Design, 2017

SAT-Based Generation of Optimum Function Implementations with XOR Gates.

Petr Fiser, Ivo Hálecek, Jan Schmidt

Proceedings of the Euromicro Conference on Digital System Design, 2017

Are XORs in logic synthesis really necessary?

Ivo Hálecek, Petr Fiser, Jan Schmidt

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016

Error Correction Method Based on the Short-Duration Offline Test.

Jan Belohoubek, Petr Fiser, Jan Schmidt

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

A new method for path criticality calculation.

Róbert Tamási, Miroslav Siebert, Elena Gramatová, Petr Fiser

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

A new user-friendly ATPG platform for digital circuits.

Marek Lipovský, Ján Svarc, Elena Gramatová, Petr Fiser

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

A rule-based approach for minimizing power dissipation of digital circuits.

Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy.

Jan Belohoubek, Petr Fiser, Jan Schmidt

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

On don't cares in test compression.

Jirí Balcárek, Petr Fiser, Jan Schmidt

Microprocess. Microsystems, 2014

Dual-rail asynchronous logic multi-level implementation.

Igor Lemberski, Petr Fiser

Integr., 2014

Asynchronous sum-of-products logic minimization and orthogonalization.

Igor Lemberski, Petr Fiser, Ruslan Suleimanov

Int. J. Circuit Theory Appl., 2014

On Robustness of EDA Tools.

Jan Schmidt, Petr Fiser, Jiri Balcarek

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

PBO-Based Test Compression.

Jiri Balcarek, Petr Fiser, Jan Schmidt

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Sources of bias in EDA tools and its influence.

Petr Fiser, Jan Schmidt, Jiri Balcarek

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

The influence of implementation type on dependability parameters.

Jan Schmidt, Petr Fiser, Jiri Balcarek

Microprocess. Microsystems, 2013

Techniques for SAT-based constrained test pattern generation.

Jiri Balcarek, Petr Fiser, Jan Schmidt

Microprocess. Microsystems, 2013

Simulation and SAT Based ATPG for Compressed Test Generation.

Jiri Balcarek, Petr Fiser, Jan Schmidt

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

The Influence of Implementation Technology on Dependability Parameters.

Jan Schmidt, Petr Fiser, Jiri Balcarek

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Improving the iterative power of resynthesis.

Petr Fiser, Jan Schmidt

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2010

Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints.

Igor Lemberski, Petr Fiser

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG.

Jiri Balcarek, Petr Fiser, Jan Schmidt

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

On logic synthesis of conventionally hard to synthesize circuits using genetic programming.

Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

The Case for a Balanced Decomposition Process.

Jan Schmidt, Petr Fiser

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms.

Petr Fiser, David Toman

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Asynchronous two-level logic of reduced cost.

Igor Lemberski, Petr Fiser

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

Column-matching based mixed-mode test pattern generator design technique for BIST.

Petr Fiser, Hana Kubátová

Microprocess. Microsystems, 2008

An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA.

Petr Fiser, Pavel Kubalík, Hana Kubátová

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Fast Boolean Minimizer for Completely Specified Functions.

Petr Fiser, Pemysl Rucký, Irena Vanová

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

Pseudo-Random Pattern Generator Design for Column-Matching BIST.

Petr Fiser

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

Fault Tolerant System Design Method Based on Self-Checking Circuits.

Pavel Kubalík, Petr Fiser, Hana Kubátová

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications.

Petr Fiser, Hana Kubátová

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Multiple-Vector Column-Matching BIST Design Method.

Petr Fiser, Hana Kubátová

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2004

Survey of the Algorithms in the Column-Matching BIST Method.

Petr Fiser, Hana Kubátová

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Boolean Minimizer FC-Min: Coverage Finding Process.

Petr Fiser, Hana Kubátová

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003

BOOM - A Heuristic Boolean Minimizer.

Jan Hlavicka, Petr Fiser

Comput. Artif. Intell., 2003

FC-Min: A Fast Multi-Output Boolean Minimizer.

Petr Fiser, Jan Hlavicka, Hana Kubátová

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002

Minimization and Partitioning Method Reducing Input Sets.

Jan Hlavicka, Petr Fiser

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001

On the Use of Mutations in Boolean Minimization.

Petr Fiser, Jan Hlavicka

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001