Petr Fiser

Orcid: 0000-0001-5306-6343

According to our database1, Petr Fiser authored at least 59 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
On the Influence of the Laser Illumination on the Logic Cells Current Consumption.
CoRR, 2024

Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Adaptive Input Normalization for Quantized Neural Networks.
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks.
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

2023
Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring.
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023

On the Influence of the Laser Illumination on the Logic Cells Current Consumption : First measurement results.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Reducing Output Response Aliasing Using Boolean Optimization Techniques.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022
A Design Space Exploration Framework for Memristor-Based Crossbar Architecture.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021
Minimization of Switching Activity of Graphene Based Circuits.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Emerging Technologies: Challenges and Opportunities for Logic Synthesis.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
Special issue on DSD 2018.
Microprocess. Microsystems, 2020

Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Standard Cell Tuning Enables Data-Independent Static Power Consumption.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019
SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support.
J. Circuits Syst. Comput., 2019

CMOS Illumination Discloses Processed Data.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Using Voters May Lead to Secret Leakage.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018
Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR.
Microelectron. Reliab., 2018

ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction.
Microprocess. Microsystems, 2018

Optimum polymorphic circuits synthesis method.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Synthesis of Finite State Machines on Memristor Crossbars.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
Error masking method based on the short-duration offline test.
Microprocess. Microsystems, 2017

SAT-Based ATPG for Zero-Aliasing Compaction.
Proceedings of the Euromicro Conference on Digital System Design, 2017

SAT-Based Generation of Optimum Function Implementations with XOR Gates.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Are XORs in logic synthesis really necessary?
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Error Correction Method Based on the Short-Duration Offline Test.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

A new method for path criticality calculation.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

A new user-friendly ATPG platform for digital circuits.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

A rule-based approach for minimizing power dissipation of digital circuits.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
On don't cares in test compression.
Microprocess. Microsystems, 2014

Dual-rail asynchronous logic multi-level implementation.
Integr., 2014

Asynchronous sum-of-products logic minimization and orthogonalization.
Int. J. Circuit Theory Appl., 2014

On Robustness of EDA Tools.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

PBO-Based Test Compression.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Sources of bias in EDA tools and its influence.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
The influence of implementation type on dependability parameters.
Microprocess. Microsystems, 2013

Techniques for SAT-based constrained test pattern generation.
Microprocess. Microsystems, 2013

Simulation and SAT Based ATPG for Compressed Test Generation.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
The Influence of Implementation Technology on Dependability Parameters.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Improving the iterative power of resynthesis.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2010
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

On logic synthesis of conventionally hard to synthesize circuits using genetic programming.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
The Case for a Balanced Decomposition Process.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Asynchronous two-level logic of reduced cost.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008
Column-matching based mixed-mode test pattern generator design technique for BIST.
Microprocess. Microsystems, 2008

An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Fast Boolean Minimizer for Completely Specified Functions.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
Pseudo-Random Pattern Generator Design for Column-Matching BIST.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Fault Tolerant System Design Method Based on Self-Checking Circuits.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Multiple-Vector Column-Matching BIST Design Method.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2004
Survey of the Algorithms in the Column-Matching BIST Method.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Boolean Minimizer FC-Min: Coverage Finding Process.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003
BOOM - A Heuristic Boolean Minimizer.
Comput. Artif. Intell., 2003

FC-Min: A Fast Multi-Output Boolean Minimizer.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002
Minimization and Partitioning Method Reducing Input Sets.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2001
On the Use of Mutations in Boolean Minimization.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001


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