Peter Zipf
Orcid: 0000-0003-4725-4246Affiliations:
- University of Kassel, Germany
According to our database1,
Peter Zipf
authored at least 103 papers
between 2000 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
2023
ACM Trans. Reconfigurable Technol. Syst., September, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022
2021
Proceedings of the IEEE International Conference on Autonomic Computing and Self-Organizing Systems, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Computers, 2017
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017
Proceedings of the International Conference on Field Programmable Technology, 2017
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017
2016
Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs".
Int. J. Reconfigurable Comput., 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
2015
Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits.
CoRR, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015
2014
Dynamically Reconfigurable Constant Multiplication on FPGAs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014
Efficient High Speed Compression Trees on Xilinx FPGAs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
EURASIP J. Adv. Signal Process., 2013
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Reduced complexity single and multiple constant multiplication in floating point precision.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
2011
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the Dynamically Reconfigurable Systems - Architectures, 2010
2009
On the design of reconfigurable multipliers for integer and Galois field multiplication.
Microprocess. Microsystems, 2009
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips.
Int. J. Reconfigurable Comput., 2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
2007
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme).
it Inf. Technol., 2007
A Customizable LEON2-Based VLIW Processor.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007
A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
Proceedings of the FPL 2007, 2007
2006
A Concept for a Profile-based Dynamic Reconfiguration Mechanism.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Eine Scheduling Heuristik zur Minimierung der Verlustleistung.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006
Proceedings of the ARCS 2006, 2006
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
2005
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.
Proceedings of the Embedded Computer Systems: Architectures, 2005
Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005
A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
An Asynchronous Switch Implmentation for Systems-on-a-Chip.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
Flexible Overhead Processing Architectures for G.709 Optical Transport Networks.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Dynamic power optimization of the trace-back process for the Viterbi algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the Field Programmable Logic and Application, 2004
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing.
Proceedings of the First Conference on Computing Frontiers, 2004
Proceedings of the First Conference on Computing Frontiers, 2004
2003
An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders.
Proceedings of the IFIP VLSI-SoC 2003, 2003
A hierarchical generic approach for on-chip communication, testing and debugging of SoCs.
Proceedings of the IFIP VLSI-SoC 2003, 2003
An Integrated Model Bridging the Gap between Technology and Economy.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
2000
Integration und Fehlertoleranz im Codesign.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000
Proceedings of the Field-Programmable Logic and Applications, 2000