Peter Wohl

According to our database, Peter Wohl authored at least 41 papers between 1990 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

XLBIST: X-Tolerant Logic BIST.

Peter Wohl, John A. Waicukauski, Gregory A. Maston, Jonathon E. Colburn

Proceedings of the IEEE International Test Conference, 2018

2017

A New Paradigm for Synthesis of Linear Decompressors.

Emil Gizdarski, Peter Wohl, John A. Waicukauski

Proceedings of the 54th Annual Design Automation Conference, 2017

2014

Achieving extreme scan compression for SoC Designs.

Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane

Proceedings of the 2014 International Test Conference, 2014

Fault sharing in a copy-on-write based ATPG system.

X. Cai, Peter Wohl, Daniel Martin

Proceedings of the 2014 International Test Conference, 2014

2013

Improving test generation by use of majority gates.

Peter Wohl, John A. Waicukauski

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Two-level compression through selective reseeding.

Peter Wohl, John A. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, Jonathon E. Colburn

Proceedings of the 2013 IEEE International Test Conference, 2013

A distributed-multicore hybrid ATPG system.

X. Cai, Peter Wohl

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

Enhancing testability by structured partial scan.

Peter Wohl, John A. Waicukauski, Jonathon E. Colburn

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Hybrid selector for high-X scan compression.

Peter Wohl, John A. Waicukauski, Frederic Neuveux, Jonathon E. Colburn

Proceedings of the 2012 IEEE International Test Conference, 2012

2010

Increasing PRPG-based compression by delayed justification.

Peter Wohl, John A. Waicukauski, T. Finklea

Proceedings of the 2011 IEEE International Test Conference, 2010

Highly efficient parallel ATPG based on shared memory.

X. Cai, Peter Wohl, John A. Waicukauski, Pramod Notiyath

Proceedings of the 2011 IEEE International Test Conference, 2010

Fully X-tolerant, very high scan compression.

Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski

Proceedings of the 47th Design Automation Conference, 2010

2008

Increasing Scan Compression by Using X-chains.

Peter Wohl, John A. Waicukauski, Frederic Neuveux

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

DFT MAX and Power.

Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri

J. Low Power Electron., 2007

Automated Design and Insertion of Optimal One-Hot Bus Encoders.

Peter Wohl, John A. Waicukauski, Sanjay Patel

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Minimizing the Impact of Scan Compression.

Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Fully X-tolerant combinational scan compression.

Peter Wohl, John A. Waicukauski, Sanjay Ramnath

Proceedings of the 2007 IEEE International Test Conference, 2007

2005

Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST.

Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Efficient compression of deterministic patterns into multiple PRPG seeds.

Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Scalable selector architecture for x-tolerant deterministic BIST.

Peter Wohl, John A. Waicukauski, Sanjay Patel

Proceedings of the 41th Design Automation Conference, 2004

2003

Analysis and Design of Optimal Combinational Compactors.

Peter Wohl, Leendert M. Huisman

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture.

Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Efficient compression and application of deterministic patterns in a logic BIST architecture.

Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin

Proceedings of the 40th Design Automation Conference, 2003

2002

Effective diagnostics through interval unloads in a BIST environment.

Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston

Proceedings of the 39th Design Automation Conference, 2002

2001

Design of compactors for signature-analyzers in built-in self-test.

Peter Wohl, John A. Waicukauski, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

P1450.1: STIL for the Simulation Environmen.

Peter Wohl, Nathan Biggs

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Optimizing the flattened test-generation model for very large designs.

Peter Wohl, John A. Waicukauski

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

Using Verilog simulation libraries for ATPG.

Peter Wohl, John A. Waicukauski

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Output in still, input in still.

Peter Wohl

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Defining ATPG rules checking in STIL.

Peter Wohl, John A. Waicukauski

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Extracting gate-level networks from simulation tables.

Peter Wohl, John A. Waicukauski

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Using ATPG for clock rules checking in complex scan design.

Peter Wohl, John A. Waicukauski

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

A Unified Interface for Scan Test Generation Based on STIL.

Peter Wohl, John A. Waicukauski

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996

Testing "untestable" faults in three-state circuits.

Peter Wohl, John A. Waicukauski, Matthew Graf

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates.

Peter Wohl, John A. Waicukauski

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1993

Efficiency through Reduced Communication in Message Passing Simulation of Neural Networks.

Peter Wohl

Int. J. Artif. Intell. Tools, 1993

1992

Designing Conceptual Clustering for Parallel Implementation.

Peter Wohl, Thomas W. Christopher

Proceedings of the 1992 International Conference on Parallel Processing, 1992

1991

A Parallel Processing Approach to Incremental Conceptual Clustering.

Peter Wohl, Thomas W. Christopher

Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

MIMD implementation of neural networks through pipelined, parallel communication trees.

Peter Wohl, Thomas W. Christopher

Proceedings of the Third International Conference on Tools for Artificial Intelligence, 1991

Parallel Conceptual Clustering through Message-Driven Computing.

Peter Wohl, Thomas W. Christopher

Proceedings of the International Conference on Parallel Processing, 1991

1990

SIMD Neural Net Mapping on MIMD Architectures.

Peter Wohl, Thomas W. Christopher

Proceedings of the 1990 International Conference on Parallel Processing, 1990