Peter W. Cook
According to our database1,
Peter W. Cook
authored at least 13 papers
between 1984 and 2003.
Collaborative distances:
Collaborative distances:
Timeline
1984
1986
1988
1990
1992
1994
1996
1998
2000
2002
0
1
2
3
4
5
2
1
1
1
1
2
3
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2003
Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz.
IEEE J. Solid State Circuits, 2003
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology.
Proceedings of the ESSCIRC 2003, 2003
2002
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
2001
A circuit level implementation of an adaptive issue queue for power-aware microprocessors.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
2000
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro, 2000
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000
1998
Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor.
IEEE J. Solid State Circuits, 1998
1990
IEEE J. Solid State Circuits, October, 1990
1984