Peter Verplaetse

According to our database1, Peter Verplaetse authored at least 11 papers between 1998 and 2003.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2003
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Hardware implementation of an EAN-13 bar code decoder.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Getting more out of Donath's hierarchical model for interconnect prediction.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

2001
A stochastic model for the interconnection topology of digital circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2001

On partitioning vs. placement rent properties.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

On rent's rule for rectangular regions.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Refinements of Rent's Rule Allowing Accurate Interconnect Complexity Modeling.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000
Generating synthetic benchmark circuits for evaluating CAD tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

On synthetic benchmark generation methods.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools.
Proceedings of the 1999 International Symposium on Physical Design, 1999

1998
ESCAPE: environment for the simulation of computer architectures for the purpose of education.
Proceedings of the 1998 workshop on Computer architecture education, 1998


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