Peter Verplaetse
According to our database1,
Peter Verplaetse
authored at least 11 papers
between 1998 and 2003.
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Bibliography
2003
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 1999 International Symposium on Physical Design, 1999
1998
ESCAPE: environment for the simulation of computer architectures for the purpose of education.
Proceedings of the 1998 workshop on Computer architecture education, 1998