Peter Suaris

According to our database, Peter Suaris authored at least 16 papers between 1989 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2010

Application of 3-D ICs to FPGAs.

Peter Ramyalal Suaris

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

2007

Efficient Timing Analysis With Known False Paths Using Biclique Covering.

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2005

Unified quadratic programming approach for mixed mode placement.

Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris

Proceedings of the 2005 International Symposium on Physical Design, 2005

Improving the efficiency of static timing analysis with false paths.

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Total power-optimal pipelining and parallel processing under process variations in nanometer technology.

Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

The effect of post-layout pin permutation on timing.

Yuzheng Ding, Peter Suaris, Nan-Chi Chou

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

A practical cut-based physical retiming algorithm for field programmable gate arrays.

Peter Suaris, Dongsheng Wang, Nan-Chi Chou

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Incremental physical resynthesis for timing optimization.

Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Fast adders in modern FPGAs.

Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003

A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages.

Dongsheng Wang, Peter Suaris, Nan-Chi Chou

Proceedings of the Integrated Circuit and System Design, 2003

A physical retiming algorithm for field programmable gate arrays.

Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

An algebraic multigrid solver for analytical placement with layout based clustering.

Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu

Proceedings of the 40th Design Automation Conference, 2003

2000

Fast post-placement rewiring using easily detectable functional symmetries.

Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska

Proceedings of the 37th Conference on Design Automation, 2000

1997

Interface Timing Verification Drives System Design.

Ajay J. Daga, Peter Suaris

Proceedings of the 34st Conference on Design Automation, 1997

1994

A Methodology and Algorithms for Post-Placement Delay Optimization.

Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang

Proceedings of the 31st Conference on Design Automation, 1994

1989

A quadrisection-based combined place and route scheme for standard cells.

Peter Ramyalal Suaris, Gershon Kedem

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989