Peter Shah

According to our database1, Peter Shah authored at least 7 papers between 1994 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2015
Lamassu: Storage-Efficient Host-Side Encryption.
Proceedings of the 2015 USENIX Annual Technical Conference, 2015

2004
A calibration method for PLLs based on transient response.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Analytical model and behavioral simulation approach for a ΣΔ fractional-N synthesizer employing a sample-hold element.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

A spur-free fractional-N ΣΔ PLL for GSM applications: linear model and simulations.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

1995
A New BiCMOS Technique for Very Fast Discrete-Time Signal Processing.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Dynamic Range of Low-Voltage Cascode Current Mirrors.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Trading Off Sspeed Versus Dynamic Range in Switched Current Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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