Peter Pridnig

According to our database1, Peter Pridnig authored at least 4 papers between 2008 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
An all-digital PLL using random modulation for SSC generation in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2009
A 1.2 V 4.5 mW 10 bit 8 MS/s cyclic-ADC for mobile video and sensor applications.
Elektrotech. Informationstechnik, 2009

A 40mW pseudo-differential 200MHz analog video pre-processing for HDTV flat-panel displays.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
A 1.2V 56mW 10 bit 165Ms/s pipeline-ADC for HD-video applications.
Proceedings of the ESSCIRC 2008, 2008


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